/dts-v1/;
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "Qualcomm Technologies, Inc. MSM cobalt";
compatible = "qcom,msmcobalt-cdp", "qcom,msmcobalt", "qcom,cdp";
qcom,msm-id = <0x124 0x0>;
interrupt-parent = <0x1>;
qcom,board-id = <0x1 0x0>;
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
qcom,limits-info = <0x2>;
enable-method = "psci";
next-level-cache = <0x3>;
qcom,ea = <0x4>;
linux,phandle = <0x14>;
phandle = <0x14>;
l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
qcom,dump-size = <0x0>;
linux,phandle = <0x3>;
phandle = <0x3>;
};
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x5f>;
phandle = <0x5f>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x67>;
phandle = <0x67>;
};
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
qcom,limits-info = <0x5>;
enable-method = "psci";
next-level-cache = <0x3>;
qcom,ea = <0x6>;
linux,phandle = <0x15>;
phandle = <0x15>;
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x60>;
phandle = <0x60>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x68>;
phandle = <0x68>;
};
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
qcom,limits-info = <0x7>;
enable-method = "psci";
next-level-cache = <0x3>;
qcom,ea = <0x8>;
linux,phandle = <0x16>;
phandle = <0x16>;
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x61>;
phandle = <0x61>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x69>;
phandle = <0x69>;
};
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
qcom,limits-info = <0x9>;
enable-method = "psci";
next-level-cache = <0x3>;
qcom,ea = <0xa>;
linux,phandle = <0x17>;
phandle = <0x17>;
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x62>;
phandle = <0x62>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
linux,phandle = <0x6a>;
phandle = <0x6a>;
};
};
cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
qcom,limits-info = <0xb>;
enable-method = "psci";
next-level-cache = <0xc>;
qcom,ea = <0xd>;
linux,phandle = <0x18>;
phandle = <0x18>;
l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
linux,phandle = <0xc>;
phandle = <0xc>;
};
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x63>;
phandle = <0x63>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x6b>;
phandle = <0x6b>;
};
};
cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
qcom,limits-info = <0xe>;
enable-method = "psci";
next-level-cache = <0xc>;
qcom,ea = <0xf>;
linux,phandle = <0x19>;
phandle = <0x19>;
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x64>;
phandle = <0x64>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x6c>;
phandle = <0x6c>;
};
};
cpu@102 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x102>;
qcom,limits-info = <0x10>;
enable-method = "psci";
next-level-cache = <0xc>;
qcom,ea = <0x11>;
linux,phandle = <0x1a>;
phandle = <0x1a>;
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x65>;
phandle = <0x65>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x6d>;
phandle = <0x6d>;
};
};
cpu@103 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x103>;
qcom,limits-info = <0x12>;
enable-method = "psci";
next-level-cache = <0xc>;
qcom,ea = <0x13>;
linux,phandle = <0x1b>;
phandle = <0x1b>;
l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x66>;
phandle = <0x66>;
};
l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
linux,phandle = <0x6e>;
phandle = <0x6e>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <0x14>;
};
core1 {
cpu = <0x15>;
};
core2 {
cpu = <0x16>;
};
core3 {
cpu = <0x17>;
};
};
cluster1 {
core0 {
cpu = <0x18>;
};
core1 {
cpu = <0x19>;
};
core2 {
cpu = <0x1a>;
};
core3 {
cpu = <0x1b>;
};
};
};
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
qcom,smp2p-modem@17911008 {
compatible = "qcom,smp2p";
reg = <0x17911008 0x4>;
qcom,remote-pid = <0x1>;
qcom,irq-bitmask = <0x4000>;
interrupts = <0x0 0x1c3 0x1>;
};
qcom,smp2p-adsp@17911008 {
compatible = "qcom,smp2p";
reg = <0x17911008 0x4>;
qcom,remote-pid = <0x2>;
qcom,irq-bitmask = <0x400>;
interrupts = <0x0 0x9e 0x1>;
};
qcom,smp2p-dsps@17911008 {
compatible = "qcom,smp2p";
reg = <0x17911008 0x4>;
qcom,remote-pid = <0x3>;
qcom,irq-bitmask = <0x4000000>;
interrupts = <0x0 0xb2 0x1>;
};
qcom,smp2pgpio-smp2p-15-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0xf>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x1c>;
phandle = <0x1c>;
};
qcom,smp2pgpio_test_smp2p_15_in {
compatible = "qcom,smp2pgpio_test_smp2p_15_in";
gpios = <0x1c 0x0 0x0>;
};
qcom,smp2pgpio-smp2p-15-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0xf>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x1d>;
phandle = <0x1d>;
};
qcom,smp2pgpio_test_smp2p_15_out {
compatible = "qcom,smp2pgpio_test_smp2p_15_out";
gpios = <0x1d 0x0 0x0>;
};
qcom,smp2pgpio-smp2p-1-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0x1>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x1e>;
phandle = <0x1e>;
};
qcom,smp2pgpio_test_smp2p_1_in {
compatible = "qcom,smp2pgpio_test_smp2p_1_in";
gpios = <0x1e 0x0 0x0>;
};
qcom,smp2pgpio-smp2p-1-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0x1>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x1f>;
phandle = <0x1f>;
};
qcom,smp2pgpio_test_smp2p_1_out {
compatible = "qcom,smp2pgpio_test_smp2p_1_out";
gpios = <0x1f 0x0 0x0>;
};
qcom,smp2pgpio-smp2p-2-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0x2>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x20>;
phandle = <0x20>;
};
qcom,smp2pgpio_test_smp2p_2_in {
compatible = "qcom,smp2pgpio_test_smp2p_2_in";
gpios = <0x20 0x0 0x0>;
};
qcom,smp2pgpio-smp2p-2-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0x2>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x21>;
phandle = <0x21>;
};
qcom,smp2pgpio_test_smp2p_2_out {
compatible = "qcom,smp2pgpio_test_smp2p_2_out";
gpios = <0x21 0x0 0x0>;
};
qcom,smp2pgpio-smp2p-3-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0x3>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x22>;
phandle = <0x22>;
};
qcom,smp2pgpio_test_smp2p_3_in {
compatible = "qcom,smp2pgpio_test_smp2p_3_in";
gpios = <0x22 0x0 0x0>;
};
qcom,smp2pgpio-smp2p-3-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <0x3>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x23>;
phandle = <0x23>;
};
qcom,smp2pgpio-ssr-smp2p-1-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "slave-kernel";
qcom,remote-pid = <0x1>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x4f>;
phandle = <0x4f>;
};
qcom,smp2pgpio-ssr-smp2p-1-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "master-kernel";
qcom,remote-pid = <0x1>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x50>;
phandle = <0x50>;
};
qcom,smp2pgpio-ssr-smp2p-2-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "slave-kernel";
qcom,remote-pid = <0x2>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x4b>;
phandle = <0x4b>;
};
qcom,smp2pgpio-ssr-smp2p-2-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "master-kernel";
qcom,remote-pid = <0x2>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x4c>;
phandle = <0x4c>;
};
qcom,smp2pgpio-ssr-smp2p-3-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "slave-kernel";
qcom,remote-pid = <0x3>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x5b>;
phandle = <0x5b>;
};
qcom,smp2pgpio-ssr-smp2p-3-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "master-kernel";
qcom,remote-pid = <0x3>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x5c>;
phandle = <0x5c>;
};
qcom,smp2pgpio_test_smp2p_3_out {
compatible = "qcom,smp2pgpio_test_smp2p_3_out";
gpios = <0x23 0x0 0x0>;
};
qcom,smp2pgpio-sleepstate-gpio-3-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "sleepstate";
qcom,remote-pid = <0x3>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x24>;
phandle = <0x24>;
};
qcom,smp2pgpio-sleepstate-3-out {
compatible = "qcom,smp2pgpio_sleepstate_3_out";
gpios = <0x24 0x0 0x0>;
};
qcom,smp2pgpio-ipa-1-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "ipa";
qcom,remote-pid = <0x1>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x33>;
phandle = <0x33>;
};
qcom,smp2pgpio-ipa-1-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "ipa";
qcom,remote-pid = <0x1>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x34>;
phandle = <0x34>;
};
qcom,gdsc@10f004 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_usb30";
reg = <0x10f004 0x4>;
status = "ok";
clock-names = "core_clk";
clocks = <0x25 0xb3b4e2cb>;
linux,phandle = <0x46>;
phandle = <0x46>;
};
qcom,gdsc@16b004 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_pcie_0";
reg = <0x16b004 0x4>;
status = "ok";
clock-names = "master_bus_clk", "slave_bus_clk", "core_clk";
clocks = <0x25 0x3f85285b 0x25 0xd69638a1 0x25 0x4f37621e>;
};
qcom,gdsc@175004 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_ufs";
reg = <0x175004 0x4>;
status = "ok";
clock-names = "bus_clk", "ice_clk", "unipro_clk";
clocks = <0x25 0x47c743a7 0x25 0x310b0710 0x25 0x2daf7fd2>;
linux,phandle = <0x41>;
phandle = <0x41>;
};
qcom,gdsc@17d034 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_hlos1_vote_lpass_adsp";
reg = <0x17d034 0x4>;
qcom,no-status-check-on-disable;
status = "ok";
linux,phandle = <0x6f>;
phandle = <0x6f>;
};
qcom,gdsc@17d038 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_hlos1_vote_lpass_core";
reg = <0x17d038 0x4>;
qcom,no-status-check-on-disable;
status = "ok";
};
qcom,gdsc@c8ce020 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_bimc_smmu";
reg = <0xc8ce020 0x4 0xc8ce024 0x4>;
reg-names = "base", "hw_ctrl_addr";
qcom,no-status-check-on-disable;
status = "ok";
clock-names = "bus_clk";
clocks = <0x26 0xc365ac39>;
linux,phandle = <0x70>;
phandle = <0x70>;
};
qcom,gdsc@c8c1024 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_venus";
reg = <0xc8c1024 0x4>;
status = "ok";
clock-names = "bus_clk", "maxi_clk", "core_clk";
clocks = <0x26 0xf3178ba5 0x26 0x1785ef88 0x26 0x78f14c85>;
linux,phandle = <0x5d>;
phandle = <0x5d>;
};
qcom,gdsc@c8c1040 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_venus_core0";
reg = <0xc8c1040 0x4>;
status = "ok";
clock-names = "core0_clk";
clocks = <0x26 0x23fae359>;
};
qcom,gdsc@c8c1044 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_venus_core1";
reg = <0xc8c1044 0x4>;
status = "ok";
clock-names = "core1_clk";
clocks = <0x26 0x5213a0c7>;
};
qcom,gdsc@c8c34a0 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_camss_top";
reg = <0xc8c34a0 0x4>;
status = "ok";
clock-names = "bus_clk", "vfe_axi";
clocks = <0x26 0xd84e390b 0x26 0xe626d8a1>;
linux,phandle = <0x27>;
phandle = <0x27>;
};
qcom,gdsc@c8c3664 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_vfe0";
reg = <0xc8c3664 0x4>;
status = "ok";
clock-names = "core0_clk", "core0_stream_clk";
clocks = <0x26 0xead28288 0x26 0xa0428287>;
parent-supply = <0x27>;
linux,phandle = <0x77>;
phandle = <0x77>;
};
qcom,gdsc@c8c3674 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_vfe1";
reg = <0xc8c3674 0x4>;
status = "ok";
clock-names = "core1_clk", "core1_stream_clk";
clocks = <0x26 0xc216b14d 0x26 0x745af3b6>;
parent-supply = <0x27>;
linux,phandle = <0x78>;
phandle = <0x78>;
};
qcom,gdsc@c8c36d4 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_cpp";
reg = <0xc8c36d4 0x4>;
status = "ok";
clock-names = "core_clk";
clocks = <0x26 0x8e99ef57>;
parent-supply = <0x27>;
linux,phandle = <0x76>;
phandle = <0x76>;
};
qcom,gdsc@c8c2304 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_mdss";
reg = <0xc8c2304 0x4>;
status = "ok";
clock-names = "bus_clk", "core_clk", "root_clk";
clocks = <0x26 0xdf04fc1d 0x26 0x43539b0e 0x26 0xbb7e71c4>;
linux,phandle = <0x119>;
phandle = <0x119>;
};
qcom,gdsc@5066004 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_gpu_cx";
reg = <0x5066004 0x4 0x5066008 0x4>;
reg-names = "base", "hw_ctrl_addr";
qcom,no-status-check-on-disable;
status = "ok";
linux,phandle = <0x72>;
phandle = <0x72>;
};
qcom,gdsc@5066094 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_gpu_gx";
reg = <0x5066094 0x4 0x5065130 0x4 0x5066090 0x4>;
reg-names = "base", "domain_addr", "sw_reset";
qcom,retain-periph;
qcom,reset-aon-logic;
status = "ok";
clock-names = "bimc_core_clk", "core_clk", "core_root_clk";
clocks = <0x25 0x3909459b 0x28 0x95f01bd5 0x28 0x917f76ef>;
qcom,force-enable-root-clk;
parent-supply = <0x29>;
linux,phandle = <0x117>;
phandle = <0x117>;
};
interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x17a00000 0x10000 0x17b00000 0x100000>;
#interrupt-cells = <0x3>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
interrupt-controller;
#redistributor-regions = <0x1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <0x1 0x9 0x4>;
linux,phandle = <0x1>;
phandle = <0x1>;
gic-its@0x17a20000 {
compatible = "arm,gic-v3-its";
msi-contoller;
reg = <0x17a20000 0x20000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x1 0x1 0xf08 0x1 0x2 0xf08 0x1 0x3 0xf08 0x1 0x0 0xf08>;
clock-frequency = <0x124f800>;
};
restart@10ac000 {
compatible = "qcom,pshold";
reg = <0x10ac000 0x4 0x1fd3000 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
qcom,sps {
compatible = "qcom,msm_sps_4k";
qcom,pipe-attr-ee;
};
serial@0c170000 {
compatible = "qcom,msm-lsuart-v14";
reg = <0xc170000 0x1000>;
interrupts = <0x0 0x6c 0x0>;
status = "disabled";
clocks = <0x25 0xf8a61c96 0x25 0x8caa5b4f>;
clock-names = "core_clk", "iface_clk";
};
serial@0c1b0000 {
compatible = "qcom,msm-lsuart-v14";
reg = <0xc1b0000 0x1000>;
interrupts = <0x0 0x72 0x0>;
status = "disabled";
clocks = <0x25 0x1e1965a3 0x25 0x8f283c1d>;
clock-names = "core_clk", "iface_clk";
};
timer@17920000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17920000 0x1000>;
clock-frequency = <0x124f800>;
frame@17921000 {
frame-number = <0x0>;
interrupts = <0x0 0x8 0x4 0x0 0x7 0x4>;
reg = <0x17921000 0x1000 0x17922000 0x1000>;
};
frame@17923000 {
frame-number = <0x1>;
interrupts = <0x0 0x9 0x4>;
reg = <0x17923000 0x1000>;
status = "disabled";
};
frame@17924000 {
frame-number = <0x2>;
interrupts = <0x0 0xa 0x4>;
reg = <0x17924000 0x1000>;
status = "disabled";
};
frame@17925000 {
frame-number = <0x3>;
interrupts = <0x0 0xb 0x4>;
reg = <0x17925000 0x1000>;
status = "disabled";
};
frame@17926000 {
frame-number = <0x4>;
interrupts = <0x0 0xc 0x4>;
reg = <0x17926000 0x1000>;
status = "disabled";
};
frame@17927000 {
frame-number = <0x5>;
interrupts = <0x0 0xd 0x4>;
reg = <0x17927000 0x1000>;
status = "disabled";
};
frame@17928000 {
frame-number = <0x6>;
interrupts = <0x0 0xe 0x4>;
reg = <0x17928000 0x1000>;
status = "disabled";
};
};
qcom,cpubw {
compatible = "qcom,devbw";
governor = "performance";
qcom,src-dst-ports = <0x1 0x200>;
qcom,active-only;
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>;
};
qcom,mincpubw {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <0x1 0x200>;
qcom,active-only;
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>;
linux,phandle = <0x2c>;
phandle = <0x2c>;
};
qcom,memlat-cpu0 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <0x1 0x200>;
qcom,active-only;
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>;
linux,phandle = <0x2a>;
phandle = <0x2a>;
};
qcom,memlat-cpu4 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <0x1 0x200>;
qcom,active-only;
qcom,bw-tbl = <0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>;
linux,phandle = <0x2b>;
phandle = <0x2b>;
};
qcom,arm-memlat-mon-0 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <0x14 0x15 0x16 0x17>;
qcom,target-dev = <0x2a>;
};
qcom,arm-memlat-mon-4 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <0x18 0x19 0x1a 0x1b>;
qcom,target-dev = <0x2b>;
};
devfreq-cpufreq {
mincpubw-cpufreq {
target-dev = <0x2c>;
cpu-to-dev-map-0 = <0x1cb600 0x5f5>;
cpu-to-dev-map-4 = <0x1ec300 0x5f5 0x1fef00 0x144b>;
};
};
qcom,msm-cpufreq {
compatible = "qcom,msm-cpufreq";
clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk", "cpu4_clk", "cpu5_clk", "cpu6_clk", "cpu7_clk";
clocks = <0x2d 0xc554130e 0x2d 0xc554130e 0x2d 0xc554130e 0x2d 0xc554130e 0x2d 0x58869997 0x2d 0x58869997 0x2d 0x58869997 0x2d 0x58869997>;
qcom,governor-per-policy;
qcom,cpufreq-table-0 = <0x493e0 0x54600 0x67200 0x79e00 0x8ca00 0x9ab00 0xad700 0xc4e00 0xd7a00 0xea600 0xfd200 0x10fe00 0x122a00 0x130b00 0x143700 0x156300 0x168f00 0x180600 0x193200 0x1a5e00 0x1b8a00 0x1cb600>;
qcom,cpufreq-table-4 = <0x493e0 0x54600 0x67200 0x75300 0x87f00 0x9ab00 0xad700 0xc0300 0xce400 0xdc500 0xef100 0x101d00 0x11df00 0x130b00 0x143700 0x156300 0x168f00 0x177000 0x18e700 0x1a1300 0x1b3f00 0x1c6b00 0x1d9700 0x1ec300 0x1fef00>;
};
arm64-cpu-erp {
compatible = "arm,arm64-cpu-erp";
interrupts = <0x0 0x2b 0x4 0x0 0x2c 0x4 0x0 0x29 0x4 0x0 0x2a 0x4>;
interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq";
poll-delay-ms = <0x1388>;
};
qcom,gcc@100000 {
compatible = "qcom,gcc-cobalt";
reg = <0x100000 0xb0000>;
reg-names = "cc_base";
vdd_dig-supply = <0x2e>;
#clock-cells = <0x1>;
linux,phandle = <0x25>;
phandle = <0x25>;
};
qcom,mmsscc@c8c0000 {
compatible = "qcom,mmsscc-cobalt";
reg = <0xc8c0000 0x40000>;
reg-names = "cc_base";
vdd_dig-supply = <0x2e>;
clock-names = "xo", "gpll0", "gpll0_div";
clocks = <0x25 0x79e95308 0x25 0xe9374de7 0x25 0xdd06848d>;
#clock-cells = <0x1>;
linux,phandle = <0x26>;
phandle = <0x26>;
};
qcom,gpucc@5065000 {
compatible = "qcom,gpucc-cobalt";
reg = <0x5065000 0x9000>;
reg-names = "cc_base";
vdd_gpucc-supply = <0x29>;
vdd_dig-supply = <0x2e>;
vdd_mx-supply = <0x2f>;
vdd_gpu_mx-supply = <0x2f>;
qcom,gfx3d_clk_src-opp-store-vcorner = <0x30>;
clock-names = "xo_ao", "gpll0";
clocks = <0x25 0x64eb6004 0x25 0xe9374de7>;
qcom,gfxfreq-speedbin0 = <0x0 0x0 0x0 0xa3140c0 0x7ef40 0x80 0xef5f4c0 0x8b290 0x80 0x13c9eb00 0x99cf0 0x80 0x18054ac0 0xa6040 0x80 0x1e0a6e00 0xb5e28 0x100 0x26be3680 0xd0bd8 0x180>;
qcom,gfxfreq-mx-speedbin0 = <0x0 0x0 0xa3140c0 0x80 0xef5f4c0 0x80 0x13c9eb00 0x80 0x18054ac0 0x80 0x1e0a6e00 0x100 0x26be3680 0x180>;
#clock-cells = <0x1>;
linux,phandle = <0x28>;
phandle = <0x28>;
};
qcom,cpu-clock-cobalt@179c0000 {
compatible = "qcom,cpu-clock-osm";
reg = <0x179c0000 0x4000 0x17916000 0x1000 0x17816000 0x1000>;
reg-names = "osm", "pwrcl_pll", "perfcl_pll";
vdd-pwrcl-supply = <0x31>;
vdd-perfcl-supply = <0x32>;
interrupts = <0x0 0x23 0x1 0x0 0x24 0x1>;
interrupt-names = "pwrcl-irq", "perfcl-irq";
qcom,pwrcl-speedbin0-v0 = <0x11e1a300 0x4000f 0x31e001e 0x1 0x14997000 0x5040012 0x4200020 0x1 0x192d5000 0x5040016 0x4200020 0x1 0x1dc13000 0x504001a 0x5200020 0x1 0x22551000 0x504001e 0x6200020 0x1 0x25c3f800 0x4040021 0x7200020 0x1 0x2a57d800 0x4040025 0x7200020 0x1 0x3010b000 0x404002a 0x8220022 0x2 0x34a49000 0x404002e 0x9250025 0x2 0x39387000 0x4040032 0xa280028 0x2 0x3dcc5000 0x4040036 0xb2b002b 0x3 0x42603000 0x404003a 0xc2e002e 0x3 0x46f41000 0x404003e 0xc320032 0x3 0x4a62f800 0x4040041 0xd340034 0x3 0x4ef6d800 0x4040045 0xe370037 0x3 0x538ab800 0x4040049 0xf3a003a 0x3 0x581e9800 0x404004d 0x103e003e 0x3 0x5dd77000 0x4040052 0x10420042 0x4 0x626b5000 0x4040056 0x11450045 0x4 0x66ff3000 0x404005a 0x12480048 0x4 0x6b931000 0x404005e 0x134b004b 0x4 0x7026f000 0x4040062 0x144e004e 0x4>;
qcom,perfcl-speedbin0-v0 = <0x11e1a300 0x4000f 0x3200020 0x1 0x14997000 0x5040012 0x4200020 0x1 0x192d5000 0x5040016 0x4200020 0x1 0x1c9c3800 0x5040019 0x5200020 0x1 0x21301800 0x504001d 0x6200020 0x1 0x25c3f800 0x4040021 0x7200020 0x1 0x2a57d800 0x4040025 0x7200020 0x1 0x2eebb800 0x4040029 0x8210021 0x1 0x325aa000 0x404002c 0x9240024 0x2 0x35c98800 0x404002f 0x9260026 0x2 0x3a5d6800 0x4040033 0xa290029 0x2 0x3ef14800 0x4040037 0xb2c002c 0x2 0x45cf1800 0x404003d 0xc300030 0x3 0x4a62f800 0x4040041 0xd340034 0x3 0x4ef6d800 0x4040045 0xe370037 0x3 0x538ab800 0x4040049 0xf3b003b 0x3 0x581e9800 0x404004d 0xf3e003e 0x3 0x5b8d8000 0x4040050 0x10400040 0x3 0x61465800 0x4040055 0x11440044 0x4 0x65da3800 0x4040059 0x12480048 0x4 0x6a6e1800 0x404005d 0x134a004a 0x4 0x6f01f800 0x4040061 0x134e004e 0x4 0x7395d800 0x4040065 0x14510051 0x4 0x7829b800 0x4040069 0x15540054 0x4 0x7cbd9800 0x404006d 0x16570057 0x4>;
qcom,osm-pll-setup;
qcom,up-timer = <0x1 0x1>;
qcom,down-timer = <0x1 0x1>;
qcom,pc-override-index = <0x0 0x0>;
qcom,set-ret-inactive;
qcom,enable-llm-freq-vote;
qcom,llm-freq-up-timer = <0x1 0x1>;
qcom,llm-freq-down-timer = <0x1 0x1>;
qcom,enable-llm-volt-vote;
qcom,llm-volt-up-timer = <0x1 0x1>;
qcom,llm-volt-down-timer = <0x1 0x1>;
qcom,cc-reads = <0xa>;
qcom,cc-delay = <0x5>;
qcom,cc-factor = <0x64>;
qcom,osm-clk-rate = <0xbebc200>;
qcom,xo-clk-rate = <0x124f800>;
qcom,l-val-base = <0x17916004 0x17816004>;
qcom,apcs-itm-present = <0x179d143c 0x179d143c>;
qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>;
qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>;
qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>;
qcom,apm-mode-ctl = <0x179d0004 0x179d0010>;
qcom,apm-ctrl-status = <0x179d000c 0x179d0018>;
qcom,red-fsm-en;
qcom,boost-fsm-en;
qcom,safe-fsm-en;
qcom,ps-fsm-en;
qcom,droop-fsm-en;
qcom,wfx-fsm-en;
qcom,pc-fsm-en;
qcom,pwrcl-apcs-mem-acc-cfg = <0x179d1360 0x179d1364 0x179d1364>;
qcom,perfcl-apcs-mem-acc-cfg = <0x179d1368 0x179d136c 0x179d1370>;
qcom,pwrcl-apcs-mem-acc-val = <0x0 0x10000000 0x10000000 0x0 0x10000000 0x10000000 0x0 0x0 0x0 0x0 0x1 0x1>;
qcom,perfcl-apcs-mem-acc-val = <0x0 0x0 0x10000000 0x0 0x0 0x10000000 0x0 0x0 0x0 0x0 0x0 0x1>;
clock-names = "aux_clk", "xo_ao";
clocks = <0x25 0x17eb05d0 0x25 0x64eb6004>;
#clock-cells = <0x1>;
linux,phandle = <0x2d>;
phandle = <0x2d>;
};
qcom,debugcc@162000 {
compatible = "qcom,cc-debug-cobalt";
reg = <0x162000 0x4>;
reg-names = "cc_base";
clock-names = "debug_gpu_clk", "debug_mmss_clk";
clocks = <0x28 0x9ae8cd3c 0x26 0xe646ffda>;
#clock-cells = <0x1>;
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x200000>;
reg-names = "rmtfs";
qcom,client-id = <0x1>;
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
qcom,ipa-loaduC;
qcom,ipa-advertise-sg-support;
};
qcom,ipa@01e00000 {
compatible = "qcom,ipa";
reg = <0x1e00000 0x34000 0x1e84000 0x31fff 0x1e04000 0x2c000>;
reg-names = "ipa-base", "bam-base", "gsi-base";
interrupts = <0x0 0x14d 0x0 0x0 0x1b0 0x0 0x0 0x1b0 0x0>;
interrupt-names = "ipa-irq", "bam-irq", "gsi-irq";
qcom,ipa-hw-ver = <0xb>;
qcom,ipa-hw-mode = <0x0>;
qcom,ee = <0x0>;
qcom,use-gsi;
qcom,use-ipa-tethering-bridge;
qcom,modem-cfg-emb-pipe-flt;
qcom,do-not-use-ch-gsi-20;
qcom,ipa-wdi2;
qcom,use-64-bit-dma-mask;
clock-names = "core_clk";
clocks = <0x25 0xfa685cda>;
qcom,msm-bus,name = "ipa";
qcom,msm-bus,num-cases = <0x4>;
qcom,msm-bus,num-paths = <0x2>;
qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x0 0x0 0x5a 0x249 0x0 0x0 0x5a 0x200 0x13880 0x9c400 0x5a 0x249 0x13880 0x9c400 0x5a 0x200 0x324b0 0xea600 0x5a 0x249 0x324b0 0xea600 0x5a 0x200 0x324b0 0x36ee80 0x5a 0x249 0x324b0 0x36ee80>;
qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO";
qcom,smp2pgpio_map_ipa_1_out {
compatible = "qcom,smp2pgpio-map-ipa-1-out";
gpios = <0x33 0x0 0x0>;
};
qcom,smp2pgpio_map_ipa_1_in {
compatible = "qcom,smp2pgpio-map-ipa-1-in";
gpios = <0x34 0x0 0x0>;
};
};
qcom,ipa_fws@1e08000 {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xf>;
qcom,firmware-name = "ipa_fws";
memory-region = <0x35>;
};
qcom,chd {
compatible = "qcom,core-hang-detect";
qcom,threshold-arr = <0x179880b0 0x179980b0 0x179a80b0 0x179b80b0 0x178880b0 0x178980b0 0x178a80b0 0x178b80b0>;
qcom,config-arr = <0x179880b8 0x179980b8 0x179a80b8 0x179b80b8 0x178880b8 0x178980b8 0x178a80b8 0x178b80b8>;
};
qcom,ipc-spinlock@1f40000 {
compatible = "qcom,ipc-spinlock-sfpb";
reg = <0x1f40000 0x8000>;
qcom,num-locks = <0x8>;
};
qcom,ghd {
compatible = "qcom,gladiator-hang-detect";
qcom,threshold-arr = <0x179d141c 0x179d1420 0x179d1424 0x179d1428 0x179d142c 0x179d1430>;
qcom,config-reg = <0x179d1434>;
};
qcom,msm-gladiator-v2@17900000 {
compatible = "qcom,msm-gladiator-v2";
reg = <0x17900000 0xe000>;
reg-names = "gladiator_base";
interrupts = <0x0 0x16 0x0>;
clock-names = "atb_clk";
clocks = <0x25 0x1492202a>;
};
qcom,smem@86000000 {
compatible = "qcom,smem";
reg = <0x86000000 0x200000 0x17911008 0x4 0x778000 0x7000 0x1fd4000 0x8>;
reg-names = "smem", "irq-reg-base", "aux-mem1", "smem_targ_info_reg";
qcom,mpu-enabled;
qcom,smd-modem {
compatible = "qcom,smd";
qcom,smd-edge = <0x0>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x1000>;
interrupts = <0x0 0x1c1 0x1>;
label = "modem";
qcom,not-loadable;
};
qcom,smd-adsp {
compatible = "qcom,smd";
qcom,smd-edge = <0x1>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x100>;
interrupts = <0x0 0x9c 0x1>;
label = "adsp";
};
qcom,smd-dsps {
compatible = "qcom,smd";
qcom,smd-edge = <0x3>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x2000000>;
interrupts = <0x0 0xb0 0x1>;
label = "dsps";
};
};
qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-adsp";
qcom,fastrpc-glink;
qcom,msm_fastrpc_compute_cb1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0x8>;
};
qcom,msm_fastrpc_compute_cb2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0x9>;
};
qcom,msm_fastrpc_compute_cb3 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0xa>;
};
qcom,msm_fastrpc_compute_cb4 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0xb>;
};
qcom,msm_fastrpc_compute_cb5 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0xc>;
};
qcom,msm_fastrpc_compute_cb6 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0x5>;
};
qcom,msm_fastrpc_compute_cb7 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0x6>;
};
qcom,msm_fastrpc_compute_cb8 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <0x36 0x7>;
};
};
qcom,rpm-smd {
compatible = "qcom,rpm-glink";
qcom,glink-edge = "rpm";
rpm-channel-name = "rpm_requests";
rpm-regulator-smpa1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "rwcx";
qcom,resource-id = <0x0>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s1";
qcom,set = <0x3>;
status = "disabled";
};
regulator-s1-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s1_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-level;
linux,phandle = <0x2e>;
phandle = <0x2e>;
};
regulator-s1-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s1_floor_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
regulator-s1-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s1_level_ao";
qcom,set = <0x1>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-level;
};
};
rpm-regulator-smpa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <0x2>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s2";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x113640>;
regulator-max-microvolt = <0x113640>;
};
};
rpm-regulator-smpa3 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <0x3>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s3";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x14a140>;
regulator-max-microvolt = <0x14a140>;
qcom,init-pin-ctrl-mode = <0x4>;
linux,phandle = <0x161>;
phandle = <0x161>;
};
};
rpm-regulator-smpa4 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <0x4>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s4";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
linux,phandle = <0x45>;
phandle = <0x45>;
};
};
rpm-regulator-smpa5 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <0x5>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s5 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s5";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1f20c0>;
regulator-max-microvolt = <0x1f20c0>;
qcom,init-pin-ctrl-mode = <0x4>;
linux,phandle = <0x162>;
phandle = <0x162>;
};
};
rpm-regulator-smpa7 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <0x7>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s7 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s7";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0xfafa0>;
regulator-max-microvolt = <0xfafa0>;
qcom,init-pin-ctrl-mode = <0x1>;
};
};
rpm-regulator-smpa8 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <0x8>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s8 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s8";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0xc3500>;
regulator-max-microvolt = <0xc3500>;
};
};
rpm-regulator-smpa9 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "rwmx";
qcom,resource-id = <0x0>;
qcom,regulator-type = <0x1>;
qcom,hpm-min-load = <0x186a0>;
status = "okay";
regulator-s9 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s9";
qcom,set = <0x3>;
status = "disabled";
};
regulator-s9-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s9_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-level;
linux,phandle = <0x2f>;
phandle = <0x2f>;
};
regulator-s9-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s9_floor_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
regulator-s9-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_s9_level_ao";
qcom,set = <0x1>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-level;
};
};
rpm-regulator-ldoa1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x1>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l1";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0xd6d80>;
regulator-max-microvolt = <0xd6d80>;
linux,phandle = <0x3e>;
phandle = <0x3e>;
};
};
rpm-regulator-ldoa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x2>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l2";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x124f80>;
regulator-max-microvolt = <0x124f80>;
linux,phandle = <0x3f>;
phandle = <0x3f>;
};
};
rpm-regulator-ldoa3 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x3>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l3";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
};
};
rpm-regulator-ldoa4 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x4>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l4";
qcom,set = <0x3>;
status = "disabled";
};
regulator-l4-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l4_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-level;
};
regulator-l4-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l4_floor_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
};
rpm-regulator-ldoa5 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x5>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l5 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l5";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0xc3500>;
regulator-max-microvolt = <0xc3500>;
qcom,init-pin-ctrl-mode = <0x1>;
};
};
rpm-regulator-ldoa6 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x6>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l6 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l6";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b9680>;
regulator-max-microvolt = <0x1b9680>;
};
};
rpm-regulator-ldoa7 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x7>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l7 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l7";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
};
regulator-l7-pin-ctrl {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l7_pin_ctrl";
qcom,set = <0x3>;
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
qcom,enable-with-pin-ctrl = <0x0 0x4>;
linux,phandle = <0x163>;
phandle = <0x163>;
};
};
rpm-regulator-ldoa8 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x8>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l8 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l8";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x124f80>;
regulator-max-microvolt = <0x124f80>;
};
};
rpm-regulator-ldoa9 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x9>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l9 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l9";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b9680>;
regulator-max-microvolt = <0x2d2a80>;
};
};
rpm-regulator-ldoa10 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0xa>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l10 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l10";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b9680>;
regulator-max-microvolt = <0x2d2a80>;
};
};
rpm-regulator-ldoa11 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0xb>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l11 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l11";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
};
};
rpm-regulator-ldoa12 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0xc>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l12 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l12";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
linux,phandle = <0x49>;
phandle = <0x49>;
};
};
rpm-regulator-ldoa13 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0xd>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l13 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l13";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b9680>;
regulator-max-microvolt = <0x2d2a80>;
linux,phandle = <0x3d>;
phandle = <0x3d>;
};
};
rpm-regulator-ldoa14 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0xe>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l14 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l14";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1cafc0>;
regulator-max-microvolt = <0x1cafc0>;
};
};
rpm-regulator-ldoa15 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0xf>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l15 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l15";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
};
};
rpm-regulator-ldoa16 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x10>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l16 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l16";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x294280>;
regulator-max-microvolt = <0x294280>;
};
};
rpm-regulator-ldoa17 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x11>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l17 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l17";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x13e5c0>;
regulator-max-microvolt = <0x13e5c0>;
};
regulator-l17-pin-ctrl {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l17_pin_ctrl";
qcom,set = <0x3>;
regulator-min-microvolt = <0x13e5c0>;
regulator-max-microvolt = <0x13e5c0>;
qcom,enable-with-pin-ctrl = <0x0 0x4>;
linux,phandle = <0x164>;
phandle = <0x164>;
};
};
rpm-regulator-ldoa18 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x12>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l18 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l18";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x294280>;
regulator-max-microvolt = <0x294280>;
};
};
rpm-regulator-ldoa19 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x13>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l19 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l19";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x2de600>;
regulator-max-microvolt = <0x2de600>;
};
};
rpm-regulator-ldoa20 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x14>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l20 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l20";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x2d2a80>;
regulator-max-microvolt = <0x2d2a80>;
linux,phandle = <0x44>;
phandle = <0x44>;
};
};
rpm-regulator-ldoa21 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x15>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l21 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l21";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x2d2a80>;
regulator-max-microvolt = <0x2d2a80>;
linux,phandle = <0x3c>;
phandle = <0x3c>;
};
};
rpm-regulator-ldoa22 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x16>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l22 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l22";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x2bb380>;
regulator-max-microvolt = <0x2bb380>;
};
};
rpm-regulator-ldoa23 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x17>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l23 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l23";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x328980>;
regulator-max-microvolt = <0x328980>;
};
};
rpm-regulator-ldoa24 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x18>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l24 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l24";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x2f1e80>;
regulator-max-microvolt = <0x2f1e80>;
linux,phandle = <0x4a>;
phandle = <0x4a>;
};
};
rpm-regulator-ldoa25 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x19>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l25 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l25";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x328980>;
regulator-max-microvolt = <0x328980>;
};
regulator-l25-pin-ctrl {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l25_pin_ctrl";
qcom,set = <0x3>;
regulator-min-microvolt = <0x328980>;
regulator-max-microvolt = <0x328980>;
qcom,enable-with-pin-ctrl = <0x0 0x4>;
linux,phandle = <0x165>;
phandle = <0x165>;
};
};
rpm-regulator-ldoa26 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x1a>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l26 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l26";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x124f80>;
regulator-max-microvolt = <0x124f80>;
linux,phandle = <0x40>;
phandle = <0x40>;
};
};
rpm-regulator-ldoa27 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x1b>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l27 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l27";
qcom,set = <0x3>;
status = "disabled";
};
regulator-l27-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l27_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-level;
linux,phandle = <0x59>;
phandle = <0x59>;
};
regulator-l27-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l27_floor_level";
qcom,set = <0x3>;
regulator-min-microvolt = <0x10>;
regulator-max-microvolt = <0x180>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
};
rpm-regulator-ldoa28 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <0x1c>;
qcom,regulator-type = <0x0>;
qcom,hpm-min-load = <0x2710>;
status = "okay";
regulator-l28 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_l28";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x2de600>;
regulator-max-microvolt = <0x2de600>;
};
};
rpm-regulator-vsa1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "vsa";
qcom,resource-id = <0x1>;
qcom,regulator-type = <0x2>;
status = "okay";
regulator-lvs1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_lvs1";
qcom,set = <0x3>;
status = "okay";
};
};
rpm-regulator-vsa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "vsa";
qcom,resource-id = <0x2>;
qcom,regulator-type = <0x2>;
status = "okay";
regulator-lvs2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_lvs2";
qcom,set = <0x3>;
status = "okay";
linux,phandle = <0x5a>;
phandle = <0x5a>;
};
};
rpm-regulator-bobb {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "bobb";
qcom,resource-id = <0x1>;
qcom,regulator-type = <0x4>;
status = "okay";
regulator-bob {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_bob";
qcom,set = <0x3>;
status = "okay";
regulator-min-microvolt = <0x328980>;
regulator-max-microvolt = <0x36ee80>;
};
regulator-bob-pin1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_bob_pin1";
qcom,set = <0x3>;
regulator-min-microvolt = <0x328980>;
regulator-max-microvolt = <0x36ee80>;
qcom,use-pin-ctrl-voltage1;
linux,phandle = <0x166>;
phandle = <0x166>;
};
regulator-bob-pin2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_bob_pin2";
qcom,set = <0x3>;
regulator-min-microvolt = <0x328980>;
regulator-max-microvolt = <0x36ee80>;
qcom,use-pin-ctrl-voltage2;
};
regulator-bob-pin3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pmcobalt_bob_pin3";
qcom,set = <0x3>;
regulator-min-microvolt = <0x328980>;
regulator-max-microvolt = <0x36ee80>;
qcom,use-pin-ctrl-voltage3;
};
};
};
qcom,glink-ssr-modem {
compatible = "qcom,glink_ssr";
label = "modem";
qcom,edge = "mpss";
qcom,notify-edges = <0x37 0x38 0x39 0x3a>;
qcom,xprt = "smem";
linux,phandle = <0x3b>;
phandle = <0x3b>;
};
qcom,glink-ssr-adsp {
compatible = "qcom,glink_ssr";
label = "adsp";
qcom,edge = "lpass";
qcom,notify-edges = <0x3b 0x38 0x39 0x3a>;
qcom,xprt = "smem";
linux,phandle = <0x37>;
phandle = <0x37>;
};
qcom,glink-ssr-dsps {
compatible = "qcom,glink_ssr";
label = "slpi";
qcom,edge = "dsps";
qcom,notify-edges = <0x3b 0x37 0x39 0x3a>;
qcom,xprt = "smem";
linux,phandle = <0x38>;
phandle = <0x38>;
};
qcom,glink-ssr-rpm {
compatible = "qcom,glink_ssr";
label = "rpm";
qcom,edge = "rpm";
qcom,notify-edges = <0x37 0x3b 0x38 0x3a>;
qcom,xprt = "smem";
linux,phandle = <0x39>;
phandle = <0x39>;
};
qcom,glink-ssr-spss {
compatible = "qcom,glink_ssr";
label = "spss";
qcom,edge = "spss";
qcom,notify-edges = <0x3b 0x37 0x38 0x39>;
qcom,xprt = "mailbox";
linux,phandle = <0x3a>;
phandle = <0x3a>;
};
qcom,glink-smem-native-xprt-modem@86000000 {
compatible = "qcom,glink-smem-native-xprt";
reg = <0x86000000 0x200000 0x17911008 0x4>;
reg-names = "smem", "irq-reg-base";
qcom,irq-mask = <0x8000>;
interrupts = <0x0 0x1c4 0x1>;
label = "mpss";
};
qcom,glink-smem-native-xprt-adsp@86000000 {
compatible = "qcom,glink-smem-native-xprt";
reg = <0x86000000 0x200000 0x17911008 0x4>;
reg-names = "smem", "irq-reg-base";
qcom,irq-mask = <0x200>;
interrupts = <0x0 0x9d 0x1>;
label = "lpass";
};
qcom,glink-smem-native-xprt-dsps@86000000 {
compatible = "qcom,glink-smem-native-xprt";
reg = <0x86000000 0x200000 0x17911008 0x4>;
reg-names = "smem", "irq-reg-base";
qcom,irq-mask = <0x8000000>;
interrupts = <0x0 0xb3 0x1>;
label = "dsps";
};
qcom,glink-smem-native-xprt-rpm@778000 {
compatible = "qcom,glink-rpm-native-xprt";
reg = <0x778000 0x7000 0x17911008 0x4>;
reg-names = "msgram", "irq-reg-base";
qcom,irq-mask = <0x1>;
interrupts = <0x0 0xa8 0x1>;
label = "rpm";
};
qcom,glink-mailbox-xprt-spss@1d05008 {
compatible = "qcom,glink-mailbox-xprt";
reg = <0x1d05008 0x8 0x1d05010 0x4 0x1d0501c 0x4 0x1d06008 0x4>;
reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base", "irq-rx-reset";
qcom,irq-mask = <0x1>;
interrupts = <0x0 0x15c 0x4>;
label = "spss";
qcom,tx-ring-size = <0x800>;
qcom,rx-ring-size = <0x800>;
};
qcom,glink_pkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-loopback_cntl {
qcom,glinkpkt-transport = "lloop";
qcom,glinkpkt-edge = "local";
qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
};
qcom,glinkpkt-loopback_data {
qcom,glinkpkt-transport = "lloop";
qcom,glinkpkt-edge = "local";
qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
qcom,glinkpkt-dev-name = "glink_pkt_loopback";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
};
qcom,ipc_router {
compatible = "qcom,ipc_router";
qcom,node-id = <0x1>;
};
qcom,ipc_router_modem_xprt {
compatible = "qcom,ipc_router_glink_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "mpss";
qcom,glink-xprt = "smem";
qcom,xprt-linkid = <0x1>;
qcom,xprt-version = <0x1>;
qcom,fragmented-data;
};
qcom,ipc_router_q6_xprt {
compatible = "qcom,ipc_router_glink_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "lpass";
qcom,glink-xprt = "smem";
qcom,xprt-linkid = <0x1>;
qcom,xprt-version = <0x1>;
qcom,fragmented-data;
};
qcom,ipc_router_dsps_xprt {
compatible = "qcom,ipc_router_glink_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "dsps";
qcom,glink-xprt = "smem";
qcom,xprt-linkid = <0x1>;
qcom,xprt-version = <0x1>;
qcom,fragmented-data;
};
qcom,spcom {
compatible = "qcom,spcom";
qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
status = "ok";
};
sdhci@c0a4900 {
compatible = "qcom,sdhci-msm";
reg = <0xc0a4900 0x314 0xc0a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0x0 0x7d 0x0 0x0 0xdd 0x0>;
interrupt-names = "hc_irq", "pwr_irq";
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x23d5727f 0x25 0x861b20ac>;
qcom,large-address-bus;
qcom,bus-width = <0x4>;
qcom,cpu-dma-latency-us = <0x2bd>;
qcom,devfreq,freq-table = <0x3197500 0xbebc200>;
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <0x8>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x51 0x200 0x0 0x0 0x51 0x200 0x640 0xc80 0x51 0x200 0x13880 0x27100 0x51 0x200 0x186a0 0x30d40 0x51 0x200 0x30d40 0x61a80 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0xc3500 0xc3500 0x51 0x200 0x1f4000 0x3e8000>;
qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
status = "ok";
vdd-supply = <0x3c>;
qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>;
qcom,vdd-current-level = <0xc8 0xc3500>;
vdd-io-supply = <0x3d>;
qcom,vdd-io-voltage-level = <0x1b9680 0x2d2a80>;
qcom,vdd-io-current-level = <0xc8 0x55f0>;
qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
};
ufsphy@1da7000 {
compatible = "qcom,ufs-phy-qmp-v3";
reg = <0x1da7000 0xda8>;
reg-names = "phy_mem";
#phy-cells = <0x0>;
clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk";
clocks = <0x25 0xb867b147 0x25 0x92aa126f 0x25 0x17acc8fb>;
status = "ok";
vdda-phy-supply = <0x3e>;
vdda-pll-supply = <0x3f>;
vddp-ref-clk-supply = <0x40>;
vdda-phy-max-microamp = <0xc8c8>;
vdda-pll-max-microamp = <0x3908>;
vddp-ref-clk-max-microamp = <0x64>;
vddp-ref-clk-always-on;
linux,phandle = <0x42>;
phandle = <0x42>;
};
ufsice@1db0000 {
compatible = "qcom,ice";
reg = <0x1db0000 0x8000>;
qcom,enable-ice-clk;
clock-names = "ufs_core_clk", "bus_clk", "iface_clk", "ice_core_clk";
clocks = <0x25 0x47c743a7 0x25 0x873459d8 0x25 0x1914bb84 0x25 0x310b0710>;
qcom,op-freq-hz = <0x0 0x0 0x0 0x11e1a300>;
vdd-hba-supply = <0x41>;
qcom,msm-bus,name = "ufs_ice_noc";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x1 0x28a 0x0 0x0 0x1 0x28a 0x3e8 0x0>;
qcom,bus-vector-names = "MIN", "MAX";
qcom,instance-type = "ufs";
status = "ok";
linux,phandle = <0x43>;
phandle = <0x43>;
};
ufshc@1da4000 {
compatible = "jedec,ufs-1.1";
reg = <0x1da4000 0x2500>;
interrupts = <0x0 0x109 0x0>;
phys = <0x42>;
phy-names = "ufsphy";
ufs-qcom-crypto = <0x43>;
clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk";
clocks = <0x25 0x47c743a7 0x25 0x873459d8 0x25 0x1914bb84 0x25 0x2daf7fd2 0x25 0x310b0710 0x25 0xb867b147 0x25 0x6a9f747a 0x25 0x7f43251c>;
freq-table-hz = <0x5f5e100 0xbebc200 0x0 0x0 0x0 0x0 0x47868c0 0x8f0d180 0x8f0d180 0x11e1a300 0x0 0x0 0x0 0x0 0x0 0x0>;
lanes-per-direction = <0x1>;
qcom,msm-bus,name = "ufs1";
qcom,msm-bus,num-cases = <0xc>;
qcom,msm-bus,num-paths = <0x2>;
qcom,msm-bus,vectors-KBps = <0x5f 0x200 0x0 0x0 0x1 0x28a 0x0 0x0 0x5f 0x200 0x39a 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x734 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0xe68 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x1cd0 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x1f334 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x3e667 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x7cccd 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x247ae 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x48ccd 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x9199a 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x3e8000 0x0 0x1 0x28a 0x3e8 0x0>;
qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "MAX";
qcom,cpu-affinity = "affine_cores";
qcom,cpu-dma-latency-us = <0x12d>;
status = "ok";
vdd-hba-supply = <0x41>;
vdd-hba-fixed-regulator;
vcc-supply = <0x44>;
vccq-supply = <0x40>;
vccq2-supply = <0x45>;
vcc-max-microamp = <0xb71b0>;
vccq-max-microamp = <0x88b80>;
vccq2-max-microamp = <0xb71b0>;
ufs_variant {
compatible = "qcom,ufs_variant";
};
};
ssusb@a800000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa800000 0xf8c00 0xc016000 0x400>;
reg-names = "core_base", "ahb2phy_base";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
interrupts = <0x0 0x85 0x0 0x0 0xb4 0x0>;
interrupt-names = "hs_phy_irq", "pwr_event_irq";
USB3_GDSC-supply = <0x46>;
qcom,msm-bus,name = "usb3";
qcom,msm-bus,num-cases = <0x3>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x0 0x0 0x3d 0x200 0x3a980 0xea600 0x3d 0x200 0x3a980 0xea600>;
qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>;
clocks = <0x25 0xb3b4e2cb 0x25 0x9ea4c2d9 0x25 0xc5c3fbe8 0x25 0xa800b65a 0x25 0xd0b65c92 0x25 0xd1231a0e 0x25 0xf79c19f6>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";
dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0xa800000 0xcd00>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x83 0x0>;
usb-phy = <0x47 0x48>;
tx-fifo-resize;
snps,usb3-u1u2-disable;
snps,nominal-elastic-buffer;
snps,hird_thresh = <0x10>;
};
};
android_usb {
compatible = "qcom,android-usb";
};
qusb@c012200 {
compatible = "qcom,qusb2phy";
reg = <0xc012200 0x2a8 0x78024c 0x4>;
reg-names = "qusb_phy_base", "tune2_efuse_addr";
vdd-supply = <0x3e>;
vdda18-supply = <0x49>;
vdda33-supply = <0x4a>;
qcom,vdd-voltage-level = <0x0 0xd6d80 0xd6d80>;
phy_type = "utmi";
clocks = <0x25 0xb867b147 0x25 0x53351d25 0x25 0xd1231a0e 0x25 0x7550fa1>;
clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset";
linux,phandle = <0x47>;
phandle = <0x47>;
};
ssphy@c010000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0xc010000 0xbf8 0x1fcb244 0x4>;
reg-names = "qmp_phy_base", "vls_clamp_reg";
vdd-supply = <0x3e>;
core-supply = <0x49>;
qcom,vdd-voltage-level = <0x0 0xd6d80 0xd6d80>;
qcom,vbus-valid-override;
clocks = <0x25 0xd9a36e0 0x25 0xf279aff2 0x25 0xd1231a0e 0x25 0x3d559f1 0x25 0xb1a4f885 0x25 0xb867b147 0x25 0xb6cc8f00>;
clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset", "phy_phy_reset", "ref_clk_src", "ref_clk";
linux,phandle = <0x48>;
phandle = <0x48>;
};
qcom,lpass@17300000 {
compatible = "qcom,pil-tz-generic";
reg = <0x17300000 0x100>;
interrupts = <0x0 0xa2 0x1>;
vdd_cx-supply = <0x2e>;
qcom,proxy-reg-names = "vdd_cx";
qcom,vdd_cx-uV-uA = <0x180 0x186a0>;
clocks = <0x25 0xe17f0ff6>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <0x1>;
qcom,proxy-timeout-ms = <0x2710>;
qcom,smem-id = <0x1a7>;
qcom,sysmon-id = <0x1>;
status = "ok";
qcom,ssctl-instance-id = <0x14>;
qcom,firmware-name = "adsp";
memory-region = <0x35>;
qcom,gpio-err-fatal = <0x4b 0x0 0x0>;
qcom,gpio-proxy-unvote = <0x4b 0x2 0x0>;
qcom,gpio-err-ready = <0x4b 0x1 0x0>;
qcom,gpio-stop-ack = <0x4b 0x3 0x0>;
qcom,gpio-force-stop = <0x4c 0x0 0x0>;
};
qcom,mss@4080000 {
compatible = "qcom,pil-q6v55-mss";
reg = <0x4080000 0x100 0x1f63000 0x8 0x1f65000 0x8 0x1f64000 0x8 0x4180000 0x20 0x179000 0x4>;
reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg";
clocks = <0x25 0x79e95308 0x25 0x111cde81 0x25 0x4325d220 0x25 0x67544d62 0x25 0xde2adeb1 0x25 0x7d794829 0x25 0xe71de85 0x25 0xf665d03f 0x25 0x1492202a>;
clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk", "qdss_clk";
qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk";
qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk";
interrupts = <0x0 0x1c0 0x1>;
vdd_cx-supply = <0x2e>;
vdd_cx-voltage = <0x180>;
vdd_mx-supply = <0x2f>;
vdd_mx-uV = <0x180>;
vdd_pll-supply = <0x4d>;
qcom,vdd_pll = <0x927c0>;
qcom,firmware-name = "modem";
qcom,pil-self-auth;
qcom,sysmon-id = <0x0>;
qcom,ssctl-instance-id = <0x12>;
qcom,override-acc;
qcom,qdsp6v62-1-2;
status = "ok";
memory-region = <0x4e>;
qcom,mem-protect-id = <0xf>;
qcom,gpio-err-fatal = <0x4f 0x0 0x0>;
qcom,gpio-err-ready = <0x4f 0x1 0x0>;
qcom,gpio-proxy-unvote = <0x4f 0x2 0x0>;
qcom,gpio-stop-ack = <0x4f 0x3 0x0>;
qcom,gpio-shutdown-ack = <0x4f 0x7 0x0>;
qcom,gpio-force-stop = <0x50 0x0 0x0>;
};
tsens@10aa000 {
compatible = "qcom,msmcobalt-tsens";
reg = <0x10aa000 0x2000 0x74230 0x1000>;
reg-names = "tsens_physical", "tsens_eeprom_physical";
interrupts = <0x0 0x1ca 0x0 0x0 0x1bd 0x0>;
interrupt-names = "tsens-upper-lower", "tsens-critical";
qcom,sensors = <0xe>;
qcom,slope = <0xb55 0xb1e 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80>;
};
tsens@10ad000 {
compatible = "qcom,msmcobalt-tsens";
reg = <0x10ad000 0x2000 0x75230 0x1000>;
reg-names = "tsens_physical", "tsens_eeprom_physical";
interrupts = <0x0 0xb8 0x0 0x0 0x1ae 0x0>;
interrupt-names = "tsens-upper-lower", "tsens-critical";
qcom,client-id = <0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15>;
qcom,sensor-id = <0x0 0x1 0x3 0x4 0x5 0x6 0x7 0x2>;
qcom,sensors = <0x8>;
qcom,slope = <0xb55 0xb1e 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80>;
};
qcom,sensor-information {
compatible = "qcom,sensor-information";
qcom,sensor-information-0 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor0";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-1 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor1";
qcom,alias-name = "pop_mem";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x51>;
phandle = <0x51>;
};
qcom,sensor-information-2 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor2";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x52>;
phandle = <0x52>;
};
qcom,sensor-information-3 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor3";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x53>;
phandle = <0x53>;
};
qcom,sensor-information-4 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor4";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x54>;
phandle = <0x54>;
};
qcom,sensor-information-5 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor5";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-6 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor6";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-7 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor7";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x55>;
phandle = <0x55>;
};
qcom,sensor-information-8 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor8";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x56>;
phandle = <0x56>;
};
qcom,sensor-information-9 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor9";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x57>;
phandle = <0x57>;
};
qcom,sensor-information-10 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor10";
qcom,scaling-factor = <0xa>;
linux,phandle = <0x58>;
phandle = <0x58>;
};
qcom,sensor-information-11 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor11";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-12 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor12";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-13 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor13";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-14 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor14";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-15 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor15";
qcom,alias-name = "gpu";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-16 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor16";
qcom,alias-name = "pop_mem";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-17 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor17";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-18 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor18";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-19 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor19";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-20 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor20";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-21 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor21";
qcom,scaling-factor = <0xa>;
};
qcom,sensor-information-22 {
qcom,sensor-type = "alarm";
qcom,sensor-name = "pm8994_tz";
qcom,scaling-factor = <0x3e8>;
};
qcom,sensor-information-23 {
qcom,sensor-type = "adc";
qcom,sensor-name = "msm_therm";
};
qcom,sensor-information-24 {
qcom,sensor-type = "adc";
qcom,sensor-name = "emmc_therm";
};
qcom,sensor-information-25 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm0";
};
qcom,sensor-information-26 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm1";
};
qcom,sensor-information-27 {
qcom,sensor-type = "adc";
qcom,sensor-name = "quiet_therm";
};
};
qseecom@86600000 {
compatible = "qcom,qseecom";
reg = <0x86600000 0x2200000>;
reg-names = "secapp-region";
qcom,hlos-num-ce-hw-instances = <0x1>;
qcom,hlos-ce-hw-instance = <0x0>;
qcom,qsee-ce-hw-instance = <0x0>;
qcom,disk-encrypt-pipe-pair = <0x2>;
qcom,support-fde;
qcom,no-clock-support;
qcom,appsbl-qseecom-support;
qcom,commonlib64-loaded-by-uefi;
qcom,msm-bus,name = "qseecom-noc";
qcom,msm-bus,num-cases = <0x4>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x0 0x0 0x37 0x200 0x1d4c0 0x124f80 0x37 0x200 0x60180 0x3c0f00>;
clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk";
clocks = <0x25 0x42229c55 0x25 0xaa858373 0x25 0x2eb28c01 0x25 0xc174dfba>;
qcom,ce-opp-freq = <0xa37d070>;
qcom,qsee-reentrancy-support = <0x2>;
};
tz-log@146BF720 {
compatible = "qcom,tz-log";
reg = <0x146bf720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom,limit_info-0 {
qcom,temperature-sensor = <0x51>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0x2>;
phandle = <0x2>;
};
qcom,limit_info-1 {
qcom,temperature-sensor = <0x52>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0x5>;
phandle = <0x5>;
};
qcom,limit_info-2 {
qcom,temperature-sensor = <0x53>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0x7>;
phandle = <0x7>;
};
qcom,limit_info-3 {
qcom,temperature-sensor = <0x54>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0x9>;
phandle = <0x9>;
};
qcom,limit_info-4 {
qcom,temperature-sensor = <0x55>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0xb>;
phandle = <0xb>;
};
qcom,limit_info-5 {
qcom,temperature-sensor = <0x56>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0xe>;
phandle = <0xe>;
};
qcom,limit_info-6 {
qcom,temperature-sensor = <0x57>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0x10>;
phandle = <0x10>;
};
qcom,limit_info-7 {
qcom,temperature-sensor = <0x58>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
linux,phandle = <0x12>;
phandle = <0x12>;
};
qcom,msm-thermal {
compatible = "qcom,msm-thermal";
qcom,sensor-id = <0x1>;
qcom,poll-ms = <0x64>;
qcom,limit-temp = <0x3c>;
qcom,temp-hysteresis = <0xa>;
qcom,therm-reset-temp = <0x73>;
qcom,freq-step = <0x4>;
qcom,core-limit-temp = <0x46>;
qcom,core-temp-hysteresis = <0xa>;
qcom,hotplug-temp = <0x46>;
qcom,hotplug-temp-hysteresis = <0x14>;
qcom,online-hotplug-core;
qcom,synchronous-cluster-id = <0x0 0x1>;
qcom,synchronous-cluster-map = <0x0 0x4 0x14 0x15 0x16 0x17 0x1 0x4 0x18 0x19 0x1a 0x1b>;
};
qcom,ssc@5c00000 {
compatible = "qcom,pil-tz-generic";
reg = <0x5c00000 0x4000>;
interrupts = <0x0 0x186 0x1>;
vdd_cx-supply = <0x59>;
vdd_px-supply = <0x5a>;
qcom,vdd_cx-uV-uA = <0x180 0x0>;
qcom,proxy-reg-names = "vdd_cx", "vdd_px";
qcom,keep-proxy-regs-on;
clocks = <0x25 0x81832015 0x25 0xaa681404>;
clock-names = "xo", "aggre2";
qcom,proxy-clock-names = "xo", "aggre2";
qcom,pas-id = <0xc>;
qcom,proxy-timeout-ms = <0x2710>;
qcom,smem-id = <0x1a8>;
qcom,sysmon-id = <0x3>;
qcom,ssctl-instance-id = <0x16>;
qcom,firmware-name = "slpi";
status = "ok";
memory-region = <0x35>;
qcom,gpio-err-fatal = <0x5b 0x0 0x0>;
qcom,gpio-proxy-unvote = <0x5b 0x2 0x0>;
qcom,gpio-err-ready = <0x5b 0x1 0x0>;
qcom,gpio-stop-ack = <0x5b 0x3 0x0>;
qcom,gpio-force-stop = <0x5c 0x0 0x0>;
};
qcom,venus@cce0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xcce0000 0x4000>;
vdd-supply = <0x5d>;
qcom,proxy-reg-names = "vdd";
clocks = <0x26 0x78f14c85 0x26 0x94334ae9 0x26 0xf3178ba5 0x26 0x1785ef88>;
clock-names = "core_clk", "iface_clk", "bus_clk", "maxi_clk";
qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", "maxi_clk";
qcom,pas-id = <0x9>;
qcom,proxy-timeout-ms = <0x64>;
qcom,firmware-name = "venus";
memory-region = <0x35>;
status = "ok";
};
qcom,wdt@17817000 {
compatible = "qcom,msm-watchdog";
reg = <0x17817000 0x1000>;
reg-names = "wdt-base";
interrupts = <0x0 0x3 0x0 0x0 0x4 0x0>;
qcom,bark-time = <0x2af8>;
qcom,pet-time = <0x2710>;
qcom,ipi-ping;
qcom,wakeup-enable;
};
qcom,spss@1d00000 {
compatible = "qcom,pil-tz-generic";
reg = <0x1d0101c 0x4 0x1d01024 0x4 0x1d01028 0x4 0x1d0103c 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err";
interrupts = <0x0 0x160 0x1>;
vdd_cx-supply = <0x2e>;
qcom,proxy-reg-names = "vdd_cx";
qcom,vdd_cx-uV-uA = <0x180 0x186a0>;
clocks = <0x25 0x5cd71a61>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pil-generic-irq-handler;
status = "ok";
qcom,pas-id = <0xe>;
qcom,proxy-timeout-ms = <0x2710>;
qcom,firmware-name = "spss";
memory-region = <0x5e>;
qcom,spss-scsr-bits = <0x0 0x1 0x2 0x3 0x10 0x11 0x18 0x19>;
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
qcom,msm-imem@146bf000 {
compatible = "qcom,msm-imem";
reg = <0x146bf000 0x1000>;
ranges = <0x0 0x146bf000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
dload_type@18 {
compatible = "qcom,msm-imem-dload-type";
reg = <0x18 0x4>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
};
cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <0x1 0x6 0x4>;
};
cpuss_dump {
compatible = "qcom,cpuss-dump";
qcom,l1_i_cache0 {
qcom,dump-node = <0x5f>;
qcom,dump-id = <0x60>;
};
qcom,l1_i_cache1 {
qcom,dump-node = <0x60>;
qcom,dump-id = <0x61>;
};
qcom,l1_i_cache2 {
qcom,dump-node = <0x61>;
qcom,dump-id = <0x62>;
};
qcom,l1_i_cache3 {
qcom,dump-node = <0x62>;
qcom,dump-id = <0x63>;
};
qcom,l1_i_cache100 {
qcom,dump-node = <0x63>;
qcom,dump-id = <0x64>;
};
qcom,l1_i_cache101 {
qcom,dump-node = <0x64>;
qcom,dump-id = <0x65>;
};
qcom,l1_i_cache102 {
qcom,dump-node = <0x65>;
qcom,dump-id = <0x66>;
};
qcom,l1_i_cache103 {
qcom,dump-node = <0x66>;
qcom,dump-id = <0x67>;
};
qcom,l1_d_cache0 {
qcom,dump-node = <0x67>;
qcom,dump-id = <0x80>;
};
qcom,l1_d_cache1 {
qcom,dump-node = <0x68>;
qcom,dump-id = <0x81>;
};
qcom,l1_d_cache2 {
qcom,dump-node = <0x69>;
qcom,dump-id = <0x82>;
};
qcom,l1_d_cache3 {
qcom,dump-node = <0x6a>;
qcom,dump-id = <0x83>;
};
qcom,l1_d_cache100 {
qcom,dump-node = <0x6b>;
qcom,dump-id = <0x84>;
};
qcom,l1_d_cache101 {
qcom,dump-node = <0x6c>;
qcom,dump-id = <0x85>;
};
qcom,l1_d_cache102 {
qcom,dump-node = <0x6d>;
qcom,dump-id = <0x86>;
};
qcom,l1_d_cache103 {
qcom,dump-node = <0x6e>;
qcom,dump-id = <0x87>;
};
};
qcom,msm-ssc-sensors {
compatible = "qcom,msm-ssc-sensors";
status = "ok";
};
qcom,msm-core@780000 {
compatible = "qcom,apss-core-ea";
reg = <0x780000 0x1000>;
qcom,low-hyst-temp = <0xa>;
qcom,high-hyst-temp = <0x5>;
qcom,polling-interval = <0x32>;
ea0 {
sensor = <0x51>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
ea1 {
sensor = <0x52>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
ea2 {
sensor = <0x53>;
linux,phandle = <0x8>;
phandle = <0x8>;
};
ea3 {
sensor = <0x54>;
linux,phandle = <0xa>;
phandle = <0xa>;
};
ea4 {
sensor = <0x55>;
linux,phandle = <0xd>;
phandle = <0xd>;
};
ea5 {
sensor = <0x56>;
linux,phandle = <0xf>;
phandle = <0xf>;
};
ea6 {
sensor = <0x57>;
linux,phandle = <0x11>;
phandle = <0x11>;
};
ea7 {
sensor = <0x58>;
linux,phandle = <0x13>;
phandle = <0x13>;
};
};
qcom,spm@178120000 {
compatible = "qcom,spm-v2";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x17812000 0x1000>;
qcom,name = "gold-l2";
qcom,saw2-ver-reg = <0xfd0>;
qcom,cpu-vctl-list = <0x18 0x19 0x1a 0x1b>;
qcom,vctl-timeout-us = <0x1f4>;
qcom,vctl-port = <0x0>;
qcom,phase-port = <0x1>;
qcom,saw2-avs-ctl = <0x1010031>;
qcom,saw2-avs-limit = <0x4000208>;
qcom,pfm-port = <0x2>;
};
qcom,spm@179120000 {
compatible = "qcom,spm-v2";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x17912000 0x1000>;
qcom,name = "silver-l2";
qcom,saw2-ver-reg = <0xfd0>;
qcom,cpu-vctl-list = <0x14 0x15 0x16 0x17>;
qcom,vctl-timeout-us = <0x1f4>;
qcom,vctl-port = <0x0>;
qcom,phase-port = <0x1>;
qcom,saw2-avs-ctl = <0x1010031>;
qcom,saw2-avs-limit = <0x4000208>;
qcom,pfm-port = <0x2>;
};
qcom,lpm-levels {
compatible = "qcom,lpm-levels";
qcom,use-psci;
#address-cells = <0x1>;
#size-cells = <0x0>;
qcom,pm-cluster@0 {
reg = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
label = "system";
qcom,spm-device-names = "cci";
qcom,psci-mode-shift = <0x8>;
qcom,psci-mode-mask = <0xf>;
qcom,pm-cluster-level@0 {
reg = <0x0>;
label = "system-wfi";
qcom,psci-mode = <0x0>;
qcom,latency-us = <0x64>;
qcom,ss-power = <0x2d5>;
qcom,energy-overhead = <0x14c08>;
qcom,time-overhead = <0x78>;
};
qcom,pm-cluster-level@1 {
reg = <0x1>;
label = "system-pc";
qcom,psci-mode = <0x3>;
qcom,latency-us = <0x15e>;
qcom,ss-power = <0x212>;
qcom,energy-overhead = <0x27100>;
qcom,time-overhead = <0x226>;
qcom,min-child-idx = <0x3>;
qcom,is-reset;
};
qcom,pm-cluster@0 {
reg = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
label = "pwr";
qcom,spm-device-names = "l2";
qcom,cpu = <0x14 0x15 0x16 0x17>;
qcom,psci-mode-shift = <0x4>;
qcom,psci-mode-mask = <0xf>;
qcom,pm-cluster-level@0 {
reg = <0x0>;
label = "pwr-l2-wfi";
qcom,psci-mode = <0x1>;
qcom,latency-us = <0x28>;
qcom,ss-power = <0x2e4>;
qcom,energy-overhead = <0xfde8>;
qcom,time-overhead = <0x55>;
};
qcom,pm-cluster-level@1 {
reg = <0x1>;
label = "pwr-l2-dynret";
qcom,psci-mode = <0x2>;
qcom,latency-us = <0x3c>;
qcom,ss-power = <0x2bc>;
qcom,energy-overhead = <0x14c08>;
qcom,time-overhead = <0x55>;
qcom,min-child-idx = <0x1>;
};
qcom,pm-cluster-level@2 {
reg = <0x2>;
label = "pwr-l2-ret";
qcom,psci-mode = <0x3>;
qcom,latency-us = <0x64>;
qcom,ss-power = <0x280>;
qcom,energy-overhead = <0x20f58>;
qcom,time-overhead = <0x55>;
qcom,min-child-idx = <0x2>;
};
qcom,pm-cluster-level@3 {
reg = <0x3>;
label = "pwr-l2-pc";
qcom,psci-mode = <0x4>;
qcom,latency-us = <0x2bc>;
qcom,ss-power = <0x1c2>;
qcom,energy-overhead = <0x33450>;
qcom,time-overhead = <0x2cec>;
qcom,min-child-idx = <0x2>;
qcom,is-reset;
};
qcom,pm-cpu {
#address-cells = <0x1>;
#size-cells = <0x0>;
qcom,psci-mode-shift = <0x0>;
qcom,psci-mode-mask = <0xf>;
qcom,pm-cpu-level@0 {
reg = <0x0>;
qcom,spm-cpu-mode = "wfi";
qcom,psci-cpu-mode = <0x1>;
qcom,latency-us = <0x14>;
qcom,ss-power = <0x2ee>;
qcom,energy-overhead = <0x7d00>;
qcom,time-overhead = <0x3c>;
};
qcom,pm-cpu-level@1 {
reg = <0x1>;
qcom,psci-cpu-mode = <0x2>;
qcom,spm-cpu-mode = "ret";
qcom,latency-us = <0x28>;
qcom,ss-power = <0x2da>;
qcom,energy-overhead = <0x14dfc>;
qcom,time-overhead = <0x6e>;
};
qcom,pm-cpu-level@2 {
reg = <0x2>;
qcom,spm-cpu-mode = "pc";
qcom,psci-cpu-mode = <0x3>;
qcom,latency-us = <0x50>;
qcom,ss-power = <0x2bc>;
qcom,energy-overhead = <0x1ee10>;
qcom,time-overhead = <0xa0>;
qcom,is-reset;
};
};
};
qcom,pm-cluster@1 {
reg = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
label = "perf";
qcom,spm-device-names = "l2";
qcom,cpu = <0x18 0x19 0x1a 0x1b>;
qcom,psci-mode-shift = <0x4>;
qcom,psci-mode-mask = <0xf>;
qcom,pm-cluster-level@0 {
reg = <0x0>;
label = "perf-l2-wfi";
qcom,psci-mode = <0x1>;
qcom,latency-us = <0x28>;
qcom,ss-power = <0x2e4>;
qcom,energy-overhead = <0x11170>;
qcom,time-overhead = <0x50>;
};
qcom,pm-cluster-level@1 {
reg = <0x1>;
label = "perf-l2-ret";
qcom,psci-mode = <0x2>;
qcom,latency-us = <0x3c>;
qcom,ss-power = <0x2bc>;
qcom,energy-overhead = <0x14c08>;
qcom,time-overhead = <0x55>;
qcom,min-child-idx = <0x1>;
};
qcom,pm-cluster-level@2 {
reg = <0x2>;
label = "perf-l2-memret";
qcom,psci-mode = <0x3>;
qcom,latency-us = <0x64>;
qcom,ss-power = <0x280>;
qcom,energy-overhead = <0x20f58>;
qcom,time-overhead = <0x55>;
qcom,min-child-idx = <0x2>;
};
qcom,pm-cluster-level@3 {
reg = <0x3>;
label = "perf-l2-pc";
qcom,psci-mode = <0x4>;
qcom,latency-us = <0x320>;
qcom,ss-power = <0x1c2>;
qcom,energy-overhead = <0x3a980>;
qcom,time-overhead = <0x2cec>;
qcom,min-child-idx = <0x2>;
qcom,is-reset;
};
qcom,pm-cpu {
#address-cells = <0x1>;
#size-cells = <0x0>;
qcom,psci-mode-shift = <0x0>;
qcom,psci-mode-mask = <0xf>;
qcom,pm-cpu-level@0 {
reg = <0x0>;
qcom,spm-cpu-mode = "wfi";
qcom,psci-cpu-mode = <0x1>;
qcom,latency-us = <0x19>;
qcom,ss-power = <0x2ee>;
qcom,energy-overhead = <0x9088>;
qcom,time-overhead = <0x32>;
};
qcom,pm-cpu-level@1 {
reg = <0x1>;
qcom,psci-cpu-mode = <0x2>;
qcom,spm-cpu-mode = "ret";
qcom,latency-us = <0x28>;
qcom,ss-power = <0x2da>;
qcom,energy-overhead = <0x14dfc>;
qcom,time-overhead = <0x6e>;
};
qcom,pm-cpu-level@2 {
reg = <0x2>;
qcom,spm-cpu-mode = "pc";
qcom,psci-cpu-mode = <0x3>;
qcom,latency-us = <0x50>;
qcom,ss-power = <0x2bc>;
qcom,energy-overhead = <0x21520>;
qcom,time-overhead = <0xa0>;
qcom,is-reset;
};
};
};
};
};
qcom,rpm-stats@200000 {
compatible = "qcom,rpm-stats";
reg = <0x200000 0x1000 0x290014 0x4 0x29001c 0x4>;
reg-names = "phys_addr_base", "offset_addr", "heap_phys_addrbase";
qcom,sleep-stats-version = <0x2>;
};
arm,smmu-anoc1@1680000 {
status = "ok";
compatible = "qcom,smmu-v2";
reg = <0x1680000 0x10000>;
#iommu-cells = <0x1>;
qcom,register-save;
qcom,skip-init;
#global-interrupts = <0x2>;
interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x16c 0x4 0x0 0x16d 0x4 0x0 0x16e 0x4 0x0 0x16f 0x4 0x0 0x170 0x4 0x0 0x171 0x4 0x0 0x172 0x4 0x0 0x1af 0x4>;
clocks = <0x25 0x49abba8>;
clock-names = "smmu_aggre1_noc_clk";
#clock-cells = <0x1>;
};
arm,smmu-anoc2@16c0000 {
status = "ok";
compatible = "qcom,smmu-v2";
reg = <0x16c0000 0x40000>;
#iommu-cells = <0x1>;
qcom,register-save;
qcom,skip-init;
#global-interrupts = <0x2>;
interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x175 0x4 0x0 0x176 0x4 0x0 0x177 0x4 0x0 0x178 0x4 0x0 0x179 0x4 0x0 0x17a 0x4 0x0 0x1ce 0x4 0x0 0x1cf 0x4 0x0 0x1d0 0x4 0x0 0x1d1 0x4 0x0 0x1d2 0x4 0x0 0x1d3 0x4 0x0 0x161 0x4 0x0 0x162 0x4 0x0 0x163 0x4 0x0 0x164 0x4 0x0 0x165 0x4 0x0 0x166 0x4 0x0 0x167 0x4 0x0 0x168 0x4>;
clocks = <0x25 0xaa681404>;
clock-names = "smmu_aggre2_noc_clk";
#clock-cells = <0x1>;
};
arm,smmu-lpass_q6@5100000 {
status = "ok";
compatible = "qcom,smmu-v2";
reg = <0x5100000 0x40000>;
#iommu-cells = <0x1>;
qcom,tz-device-id = "LPASS";
qcom,register-save;
qcom,skip-init;
#global-interrupts = <0x2>;
interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0xe2 0x4 0x0 0x189 0x4 0x0 0x18a 0x4 0x0 0x18b 0x4 0x0 0x18c 0x4 0x0 0x18d 0x4 0x0 0x18e 0x4 0x0 0x18f 0x4 0x0 0x190 0x4 0x0 0x191 0x4 0x0 0x192 0x4 0x0 0x193 0x4 0x0 0x89 0x4 0x0 0xe0 0x4 0x0 0xe1 0x4 0x0 0x136 0x4 0x0 0x194 0x4>;
vdd-supply = <0x6f>;
clocks = <0x25 0xc76f702f>;
clock-names = "lpass_q6_smmu_clk";
#clock-cells = <0x1>;
linux,phandle = <0x36>;
phandle = <0x36>;
};
arm,smmu-mmss@cd00000 {
status = "ok";
compatible = "qcom,smmu-v2";
reg = <0xcd00000 0x40000>;
#iommu-cells = <0x1>;
qcom,register-save;
qcom,skip-init;
#global-interrupts = <0x2>;
interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x107 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4 0x0 0xf4 0x4 0x0 0xf5 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4 0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4 0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4 0x0 0x104 0x4 0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x110 0x4 0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
vdd-supply = <0x70>;
clocks = <0x26 0x4825baf4 0x26 0xc365ac39>;
clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";
#clock-cells = <0x1>;
iommus = <0x71 0x1>;
linux,phandle = <0x71>;
phandle = <0x71>;
};
arm,smmu-kgsl@5040000 {
status = "ok";
compatible = "qcom,smmu-v2";
reg = <0x5040000 0x10000>;
#iommu-cells = <0x1>;
qcom-tz-device-id = "GPU";
qcom,dynamic;
qcom,register-save;
qcom,skip-init;
#global-interrupts = <0x2>;
interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x149 0x4 0x0 0x14a 0x4 0x0 0x14b 0x4 0x0 0x14c 0x4 0x0 0x74 0x4 0x0 0x75 0x4>;
vdd-supply = <0x72>;
clocks = <0x25 0x3edd69ad>;
clock-name = "kgsl_smmu_clk";
#clock-cells = <0x1>;
linux,phandle = <0x118>;
phandle = <0x118>;
};
qcom,ion {
compatible = "qcom,msm-ion";
#address-cells = <0x1>;
#size-cells = <0x0>;
qcom,ion-heap@25 {
reg = <0x19>;
qcom,ion-heap-type = "SYSTEM";
};
qcom,ion-heap@22 {
reg = <0x16>;
memory-region = <0x73>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@27 {
reg = <0x1b>;
memory-region = <0x74>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@10 {
reg = <0xa>;
memory-region = <0x75>;
qcom,ion-heap-type = "HYP_CMA";
};
qcom,ion-heap@9 {
reg = <0x9>;
qcom,ion-heap-type = "SYSTEM_SECURE";
};
};
cprh-ctrl@179c8000 {
compatible = "qcom,cprh-msmcobalt-kbss-regulator";
reg = <0x179c8000 0x4000 0x784000 0x1000>;
reg-names = "cpr_ctrl", "fuse_base";
clocks = <0x25 0x699183be>;
clock-names = "core_clk";
qcom,cpr-ctrl-name = "apc0";
qcom,cpr-controller-id = <0x0>;
qcom,cpr-sensor-time = <0x3e8>;
qcom,cpr-loop-time = <0x4c4b40>;
qcom,cpr-idle-cycles = <0xf>;
qcom,cpr-up-down-delay-time = <0xbb8>;
qcom,cpr-step-quot-init-min = <0xb>;
qcom,cpr-step-quot-init-max = <0xd>;
qcom,cpr-count-mode = <0x2>;
qcom,cpr-down-error-step-limit = <0x1>;
qcom,cpr-up-error-step-limit = <0x1>;
qcom,cpr-corner-switch-delay-time = <0x640>;
qcom,cpr-voltage-settling-time = <0x640>;
qcom,apm-threshold-voltage = <0xd0020>;
qcom,apm-hysteresis-voltage = <0xfa0>;
qcom,voltage-step = <0xfa0>;
qcom,voltage-base = <0x55f00>;
qcom,cpr-saw-use-unit-mV;
thread@0 {
qcom,cpr-thread-id = <0x0>;
qcom,cpr-consecutive-up = <0x0>;
qcom,cpr-consecutive-down = <0x2>;
qcom,cpr-up-threshold = <0x0>;
qcom,cpr-down-threshold = <0x2>;
regulator-pwrcl {
regulator-name = "apc0_pwrcl_corner";
regulator-min-microvolt = <0x1>;
regulator-max-microvolt = <0x17>;
qcom,cpr-fuse-corners = <0x4>;
qcom,cpr-fuse-combos = <0x1>;
qcom,cpr-corners = <0x16>;
qcom,cpr-corner-fmax-map = <0x7 0xa 0x11 0x16>;
qcom,cpr-voltage-ceiling = <0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xbb800 0xbb800 0xbb800 0xdac00 0xdac00 0xdac00 0xdac00 0xdac00 0xdac00 0xdac00 0xfbf40 0xfbf40 0xfbf40 0x10f7c0 0x10f7c0>;
qcom,cpr-voltage-floor = <0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8aac0 0x8aac0 0x8aac0 0xa1220 0xa1220 0xa1220 0xa1220 0xa1220 0xa1220 0xa1220 0xb7980 0xb7980 0xb7980 0xb7980 0xb7980>;
qcom,cpr-floor-to-ceiling-max-range = <0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350>;
qcom,corner-frequencies = <0x11e1a300 0x14997000 0x192d5000 0x1dc13000 0x22551000 0x25c3f800 0x2a57d800 0x3010b000 0x34a49000 0x39387000 0x3dcc5000 0x42603000 0x46f41000 0x4a62f800 0x4ef6d800 0x538ab800 0x581e9800 0x5dd77000 0x626b5000 0x66ff3000 0x6b931000 0x7026f000>;
linux,phandle = <0x31>;
phandle = <0x31>;
};
};
};
cprh-ctrl@179c4000 {
compatible = "qcom,cprh-msmcobalt-kbss-regulator";
reg = <0x179c4000 0x4000 0x784000 0x1000>;
reg-names = "cpr_ctrl", "fuse_base";
clocks = <0x25 0x699183be>;
clock-names = "core_clk";
qcom,cpr-ctrl-name = "apc1";
qcom,cpr-controller-id = <0x1>;
qcom,cpr-sensor-time = <0x3e8>;
qcom,cpr-loop-time = <0x4c4b40>;
qcom,cpr-idle-cycles = <0xf>;
qcom,cpr-up-down-delay-time = <0xbb8>;
qcom,cpr-step-quot-init-min = <0xb>;
qcom,cpr-step-quot-init-max = <0xd>;
qcom,cpr-count-mode = <0x2>;
qcom,cpr-down-error-step-limit = <0x1>;
qcom,cpr-up-error-step-limit = <0x1>;
qcom,cpr-corner-switch-delay-time = <0x640>;
qcom,cpr-voltage-settling-time = <0x640>;
qcom,apm-threshold-voltage = <0xd0020>;
qcom,apm-hysteresis-voltage = <0xfa0>;
qcom,voltage-step = <0xfa0>;
qcom,voltage-base = <0x55f00>;
qcom,cpr-saw-use-unit-mV;
thread@0 {
qcom,cpr-thread-id = <0x0>;
qcom,cpr-consecutive-up = <0x0>;
qcom,cpr-consecutive-down = <0x2>;
qcom,cpr-up-threshold = <0x0>;
qcom,cpr-down-threshold = <0x2>;
regulator-pwrcl {
regulator-name = "apc1_perfcl_corner";
regulator-min-microvolt = <0x1>;
regulator-max-microvolt = <0x1a>;
qcom,cpr-fuse-corners = <0x4>;
qcom,cpr-fuse-combos = <0x1>;
qcom,cpr-corners = <0x19>;
qcom,cpr-corner-fmax-map = <0x8 0xc 0x12 0x19>;
qcom,cpr-voltage-ceiling = <0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xa9ec0 0xbb800 0xbb800 0xbb800 0xbb800 0xdac00 0xdac00 0xdac00 0xdac00 0xdac00 0xdac00 0xfbf40 0xfbf40 0xfbf40 0xfbf40 0x10f7c0 0x10f7c0 0x10f7c0>;
qcom,cpr-voltage-floor = <0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8ba60 0x8aac0 0x8aac0 0x8aac0 0x8aac0 0xa1220 0xa1220 0xa1220 0xa1220 0xa1220 0xa1220 0xb7980 0xb7980 0xb7980 0xb7980 0xb7980 0xb7980 0xb7980>;
qcom,cpr-floor-to-ceiling-max-range = <0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350>;
qcom,corner-frequencies = <0x11e1a300 0x14997000 0x192d5000 0x1c9c3800 0x21301800 0x25c3f800 0x2a57d800 0x2eebb800 0x325aa000 0x35c98800 0x3a5d6800 0x3ef14800 0x45cf1800 0x4a62f800 0x4ef6d800 0x538ab800 0x581e9800 0x5b8d8000 0x61465800 0x65da3800 0x6a6e1800 0x6f01f800 0x7395d800 0x7829b800 0x7cbd9800>;
linux,phandle = <0x32>;
phandle = <0x32>;
};
};
};
qcom,msm-cam@8c0000 {
compatible = "qcom,msm-cam";
reg = <0x8c0000 0x40000>;
reg-names = "msm-cam";
status = "disabled";
bus-vectors = "suspend", "svs", "nominal", "turbo";
qcom,bus-votes = <0x0 0x11e1a300 0x2625a000 0x2625a000>;
};
qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu";
status = "disabled";
msm_cam_smmu_cb1 {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <0x71 0xc00 0x71 0xc01 0x71 0xc02 0x71 0xc03>;
label = "vfe";
qcom,scratch-buf-support;
};
msm_cam_smmu_cb2 {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <0x71 0xa00>;
label = "cpp";
};
msm_cam_smmu_cb3 {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <0x71 0xa01>;
label = "camera_fd";
};
msm_cam_smmu_cb4 {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <0x71 0x800>;
label = "jpeg_enc0";
};
msm_cam_smmu_cb5 {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <0x71 0x801>;
label = "jpeg_dma";
};
};
qcom,fd@caa4000 {
cell-index = <0x0>;
compatible = "qcom,face-detection";
reg = <0xcaa4000 0x800 0xcaa5000 0x400 0xca80000 0x3000>;
reg-names = "fd_core", "fd_misc", "fd_vbif";
interrupts = <0x0 0x125 0x0>;
interrupt-names = "fd";
smmu-vdd-supply = <0x70>;
camss-vdd-supply = <0x27>;
qcom,vdd-names = "smmu-vdd", "camss-vdd";
clocks = <0x26 0x120618d6 0x26 0xe4799ab7 0x26 0x749e7eb0 0x26 0x8ea480c5 0x26 0x4ff1da4d 0x26 0xa51f2c1d 0x26 0xd84e390b 0x26 0x1b33a88e>;
clock-names = "camss_top_ahb_clk", "fd_core_clk_src", "fd_core_clk", "fd_core_uar_clk", "fd_ahb_clk", "camss_ahb_clk", "camss_cpp_axi_clk", "cpp_vbif_ahb_clk";
qcom,clock-rates = <0x0 0x17d78400 0x17d78400 0x0 0x0 0x0 0x0 0x0>;
qcom,msm-bus,name = "msm_camera_fd";
qcom,msm-bus,num-cases = <0x4>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x6a 0x200 0x0 0x0 0x6a 0x200 0xc65d40 0xc65d40 0x6a 0x200 0x2aea540 0x2aea540 0x6a 0x200 0x55d4a80 0x55d4a80>;
qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000 0x24 0x10000000 0x30000000 0x28 0x10000000 0x30000000 0x2c 0x10000000 0x30000000>;
qcom,fd-misc-reg-settings = <0x20 0x2 0x3 0x24 0x2 0x3>;
status = "disabled";
};
qcom,cpp@ca04000 {
cell-index = <0x0>;
compatible = "qcom,cpp";
reg = <0xca04000 0x100 0xca80000 0x3000 0xca18000 0x3000 0xc8c36d4 0x4>;
reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
interrupts = <0x0 0x126 0x0>;
interrupt-names = "cpp";
smmu-vdd-supply = <0x70>;
camss-vdd-supply = <0x27>;
vdd-supply = <0x76>;
qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd";
clocks = <0x26 0x120618d6 0x26 0x8382f56d 0x26 0xd5554f15 0x26 0xd84e390b 0x26 0x8e99ef57 0x26 0x6c6fd3c7 0x26 0xa51f2c1d 0x26 0x1b33a88e>;
clock-names = "camss_top_ahb_clk", "cpp_core_clk", "camss_cpp_ahb_clk", "camss_cpp_axi_clk", "camss_cpp_clk", "micro_iface_clk", "camss_ahb_clk", "cpp_vbif_ahb_clk";
qcom,clock-rates = <0x0 0xbebc200 0x0 0x0 0xbebc200 0x0 0x0 0x0>;
qcom,min-clock-rate = <0xbebc200>;
qcom,bus-master = <0x1>;
qcom,vbif-qos-setting = <0x20 0x10000000 0x24 0x10000000 0x28 0x10000000 0x2c 0x10000000>;
status = "disabled";
qcom,msm-bus,name = "msm_camera_cpp";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x6a 0x200 0x0 0x0 0x6a 0x200 0x0 0x0>;
qcom,msm-bus-vector-dyn-vote;
qcom,cpp-fw-payload-info {
qcom,stripe-base = <0x316>;
qcom,plane-base = <0x2cb>;
qcom,stripe-size = <0x3f>;
qcom,plane-size = <0x19>;
qcom,fe-ptr-off = <0xb>;
qcom,we-ptr-off = <0x17>;
qcom,ref-fe-ptr-off = <0x11>;
qcom,ref-we-ptr-off = <0x24>;
qcom,we-meta-ptr-off = <0x2a>;
qcom,fe-mmu-pf-ptr-off = <0x7>;
qcom,ref-fe-mmu-pf-ptr-off = <0xa>;
qcom,we-mmu-pf-ptr-off = <0xd>;
qcom,dup-we-mmu-pf-ptr-off = <0x12>;
qcom,ref-we-mmu-pf-ptr-off = <0x17>;
qcom,set-group-buffer-len = <0x87>;
qcom,dup-frame-indicator-off = <0x46>;
};
};
qcom,ispif@ca31000 {
cell-index = <0x0>;
compatible = "qcom,ispif-v3.0", "qcom,ispif";
reg = <0xca31000 0xc00 0xca00020 0x4>;
reg-names = "ispif", "csi_clk_mux";
interrupts = <0x0 0x135 0x0>;
interrupt-names = "ispif";
qcom,num-isps = <0x2>;
camss-vdd-supply = <0x27>;
vfe0-vdd-supply = <0x77>;
vfe1-vdd-supply = <0x78>;
qcom,vdd-names = "camss-vdd", "vfe0-vdd", "vfe1-vdd";
clocks = <0x26 0x120618d6 0x26 0xa51f2c1d 0x26 0xbda4f0e3 0x26 0x227e65bc 0x26 0xccfe39ef 0x26 0x1d5bf83 0x26 0x9e26509d 0x26 0x6a2a6c36 0x26 0x3eeeaac0 0x26 0x43185024 0x26 0xf1375139 0x26 0x4113589f 0x26 0x94524569 0x26 0x4bf01dc5 0x26 0xf4de617d 0x26 0xfd934012 0x26 0x55e4bbae 0x26 0x6983a4cd 0x26 0xc166a015 0x26 0xa0c2bd8f 0x26 0xead28288 0x26 0x3b30b798 0x26 0x4e357366 0x26 0xc216b14d 0x26 0xfe729af7>;
clock-names = "camss_top_ahb_clk", "camss_ahb_clk", "ispif_ahb_clk", "csi0_src_clk", "csi0_clk", "csi0_pix_clk", "csi0_rdi_clk", "csi1_src_clk", "csi1_clk", "csi1_pix_clk", "csi1_rdi_clk", "csi2_src_clk", "csi2_clk", "csi2_pix_clk", "csi2_rdi_clk", "csi3_src_clk", "csi3_clk", "csi3_pix_clk", "csi3_rdi_clk", "vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk", "vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";
status = "disabled";
};
qcom,vfe0@ca10000 {
cell-index = <0x0>;
compatible = "qcom,vfe48";
reg = <0xca10000 0x4000 0xca40000 0x3000>;
reg-names = "vfe", "vfe_vbif";
interrupts = <0x0 0x13a 0x0>;
interrupt-names = "vfe";
vdd-supply = <0x77>;
camss-vdd-supply = <0x27>;
smmu-vdd-supply = <0x70>;
qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd";
clocks = <0x26 0x120618d6 0x26 0xa51f2c1d 0x26 0xa0c2bd8f 0x26 0xead28288 0x26 0x3b30b798 0x26 0x137bd0bd 0x26 0x109a9c6 0x26 0xa0428287 0x26 0xe626d8a1 0x26 0xc365ac39>;
clock-names = "camss_top_ahb_clk", "camss_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_csi_vfe_clk", "vfe_ahb_clk", "vfe_vbif_ahb_clk", "vfe_stream_clk", "vfe_vbif_axi_clk", "mmss_smmu_axi_clk";
qcom,clock-rates = <0x0 0x0 0x16e36000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x22551000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x23c34600 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
status = "disabled";
qos-entries = <0x8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420>;
qos-settings = <0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9>;
vbif-entries = <0x3>;
vbif-regs = <0x124 0xac 0xd0>;
vbif-settings = <0x3 0x40 0x1010>;
ds-entries = <0x11>;
ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c 0x450 0x454 0x458 0x45c 0x460 0x464>;
ds-settings = <0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0x40000103>;
qcom,msm-bus,name = "msm_camera_vfe";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x0 0x0 0x1d 0x200 0x5f5e100 0x5f5e100>;
qcom,msm-bus-vector-dyn-vote;
};
qcom,vfe1@ca14000 {
cell-index = <0x1>;
compatible = "qcom,vfe48";
reg = <0xca14000 0x4000 0xca40000 0x3000>;
reg-names = "vfe", "vfe_vbif";
interrupts = <0x0 0x13b 0x0>;
interrupt-names = "vfe";
vdd-supply = <0x78>;
camss-vdd-supply = <0x27>;
smmu-vdd-supply = <0x70>;
qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd";
clocks = <0x26 0x120618d6 0x26 0xa51f2c1d 0x26 0x4e357366 0x26 0xc216b14d 0x26 0xfe729af7 0x26 0xac0154c0 0x26 0x109a9c6 0x26 0x745af3b6 0x26 0xe626d8a1 0x26 0xc365ac39>;
clock-names = "camss_top_ahb_clk", "camss_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_csi_vfe_clk", "vfe_ahb_clk", "vfe_vbif_ahb_clk", "vfe_stream_clk", "vfe_vbif_axi_clk", "mmss_smmu_axi_clk";
qcom,clock-rates = <0x0 0x0 0x16e36000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x22551000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x23c34600 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
status = "disabled";
qos-entries = <0x8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420>;
qos-settings = <0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9>;
vbif-entries = <0x3>;
vbif-regs = <0x124 0xac 0xd0>;
vbif-settings = <0x3 0x40 0x1010>;
ds-entries = <0x11>;
ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c 0x450 0x454 0x458 0x45c 0x460 0x464>;
ds-settings = <0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0xcccc0011 0x40000103>;
qcom,msm-bus,name = "msm_camera_vfe";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x0 0x0 0x1d 0x200 0x5f5e100 0x5f5e100>;
qcom,msm-bus-vector-dyn-vote;
};
qcom,vfe {
compatible = "qcom,vfe";
num_child = <0x2>;
};
qcom,vidc@cc00000 {
compatible = "qcom,msm-vidc";
status = "disabled";
reg = <0xcc00000 0x100000>;
interrupts = <0x0 0x11f 0x4>;
qcom,max-hw-load = <0x271c80>;
qcom,hfi = "venus";
qcom,hfi-version = "3xx";
qcom,firmware-name = "venus";
qcom,never-unload-fw;
qcom,reg-presets = <0x80124 0x2000 0x80550 0x1 0x80560 0x2222221 0x80568 0x3333331 0x80570 0x1 0x80580 0x2222221 0x80588 0x3333331>;
non_secure_cb {
compatible = "qcom,msm-vidc,context-bank";
label = "venus_ns";
iommus = <0x71 0x400 0x71 0x401 0x71 0x40a 0x71 0x407 0x71 0x40e 0x71 0x40f 0x71 0x408 0x71 0x409 0x71 0x40b 0x71 0x40c 0x71 0x40d 0x71 0x410 0x71 0x421 0x71 0x428 0x71 0x429 0x71 0x42b 0x71 0x42c 0x71 0x42d 0x71 0x411 0x71 0x431>;
buffer-types = <0xfff>;
virtual-addr-pool = <0x70800000 0x8f800000>;
};
firmware_cb {
compatible = "qcom,msm-vidc,context-bank";
qcom,fw-context-bank;
iommus = <0x71 0x580 0x71 0x586>;
};
};
qcom,vmem@c880000 {
compatible = "qcom,msm-vmem";
status = "disabled";
interrupts = <0x0 0x1ad 0x4>;
reg = <0xc880000 0x6b 0x14800000 0x80000>;
reg-names = "reg-base", "mem-base";
clocks = <0x26 0x4b18955b 0x26 0xb6067889>;
clock-names = "ahb", "maxi";
qcom,msm-bus,name = "vmem";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x1 0x2c4 0x0 0x0 0x1 0x2c4 0x1f4 0x320>;
qcom,bank-size = <0x80000>;
};
tmc@6048000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b961>;
reg = <0x6048000 0x1000 0x6064000 0x15000>;
reg-names = "tmc-base", "bam-base";
arm,buffer-size = <0x400000>;
coresight-name = "coresight-tmc-etr";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
slave-mode;
remote-endpoint = <0x79>;
linux,phandle = <0x7a>;
phandle = <0x7a>;
};
};
};
replicator@6046000 {
compatible = "arm,coresight-replicator";
coresight-name = "coresight-replicator";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x7a>;
linux,phandle = <0x79>;
phandle = <0x79>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0x7b>;
linux,phandle = <0x7c>;
phandle = <0x7c>;
};
};
};
};
tmc@6047000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b961>;
reg = <0x6047000 0x1000>;
reg-names = "tmc-base";
coresight-name = "coresight-tmc-etf";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x7c>;
linux,phandle = <0x7b>;
phandle = <0x7b>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0x7d>;
linux,phandle = <0x7e>;
phandle = <0x7e>;
};
};
};
};
funnel@6045000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b908>;
reg = <0x6045000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-merg";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x7e>;
linux,phandle = <0x7d>;
phandle = <0x7d>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0x7f>;
linux,phandle = <0x81>;
phandle = <0x81>;
};
};
port@2 {
reg = <0x1>;
endpoint {
slave-mode;
remote-endpoint = <0x80>;
linux,phandle = <0x85>;
phandle = <0x85>;
};
};
};
};
funnel@6041000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b908>;
reg = <0x6041000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-in0";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x81>;
linux,phandle = <0x7f>;
phandle = <0x7f>;
};
};
port@1 {
reg = <0x3>;
endpoint {
slave-mode;
remote-endpoint = <0x82>;
linux,phandle = <0xb8>;
phandle = <0xb8>;
};
};
port@2 {
reg = <0x6>;
endpoint {
slave-mode;
remote-endpoint = <0x83>;
linux,phandle = <0x9f>;
phandle = <0x9f>;
};
};
port@3 {
reg = <0x7>;
endpoint {
slave-mode;
remote-endpoint = <0x84>;
linux,phandle = <0x96>;
phandle = <0x96>;
};
};
};
};
funnel@6042000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b908>;
reg = <0x6042000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-in1";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x85>;
linux,phandle = <0x80>;
phandle = <0x80>;
};
};
port@1 {
reg = <0x2>;
endpoint {
slave-mode;
remote-endpoint = <0x86>;
linux,phandle = <0xb2>;
phandle = <0xb2>;
};
};
port@2 {
reg = <0x3>;
endpoint {
slave-mode;
remote-endpoint = <0x87>;
linux,phandle = <0xaf>;
phandle = <0xaf>;
};
};
port@3 {
reg = <0x6>;
endpoint {
slave-mode;
remote-endpoint = <0x88>;
linux,phandle = <0x89>;
phandle = <0x89>;
};
};
};
};
funnel@7b70000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b908>;
reg = <0x7b70000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-apss-merg";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x89>;
linux,phandle = <0x88>;
phandle = <0x88>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0x8a>;
linux,phandle = <0x8d>;
phandle = <0x8d>;
};
};
port@2 {
reg = <0x1>;
endpoint {
slave-mode;
remote-endpoint = <0x8b>;
linux,phandle = <0xb5>;
phandle = <0xb5>;
};
};
port@3 {
reg = <0x3>;
endpoint {
slave-mode;
remote-endpoint = <0x8c>;
linux,phandle = <0xac>;
phandle = <0xac>;
};
};
};
};
funnel@7b60000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b908>;
reg = <0x7b60000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-apss";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x8d>;
linux,phandle = <0x8a>;
phandle = <0x8a>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0x8e>;
linux,phandle = <0x97>;
phandle = <0x97>;
};
};
port@2 {
reg = <0x1>;
endpoint {
slave-mode;
remote-endpoint = <0x8f>;
linux,phandle = <0x98>;
phandle = <0x98>;
};
};
port@3 {
reg = <0x2>;
endpoint {
slave-mode;
remote-endpoint = <0x90>;
linux,phandle = <0x99>;
phandle = <0x99>;
};
};
port@4 {
reg = <0x3>;
endpoint {
slave-mode;
remote-endpoint = <0x91>;
linux,phandle = <0x9a>;
phandle = <0x9a>;
};
};
port@5 {
reg = <0x4>;
endpoint {
slave-mode;
remote-endpoint = <0x92>;
linux,phandle = <0x9b>;
phandle = <0x9b>;
};
};
port@6 {
reg = <0x5>;
endpoint {
slave-mode;
remote-endpoint = <0x93>;
linux,phandle = <0x9c>;
phandle = <0x9c>;
};
};
port@7 {
reg = <0x6>;
endpoint {
slave-mode;
remote-endpoint = <0x94>;
linux,phandle = <0x9d>;
phandle = <0x9d>;
};
};
port@8 {
reg = <0x7>;
endpoint {
slave-mode;
remote-endpoint = <0x95>;
linux,phandle = <0x9e>;
phandle = <0x9e>;
};
};
};
};
stm@6002000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b962>;
reg = <0x6002000 0x1000 0x16280000 0x180000>;
reg-names = "stm-base", "stm-data-base";
coresight-name = "coresight-stm";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x96>;
linux,phandle = <0x84>;
phandle = <0x84>;
};
};
};
etm@7840000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7840000 0x1000>;
cpu = <0x14>;
coresight-name = "coresight-etm0";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x97>;
linux,phandle = <0x8e>;
phandle = <0x8e>;
};
};
};
etm@7940000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7940000 0x1000>;
cpu = <0x15>;
coresight-name = "coresight-etm1";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x98>;
linux,phandle = <0x8f>;
phandle = <0x8f>;
};
};
};
etm@7A40000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7a40000 0x1000>;
cpu = <0x16>;
coresight-name = "coresight-etm2";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x99>;
linux,phandle = <0x90>;
phandle = <0x90>;
};
};
};
etm@7B40000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7b40000 0x1000>;
cpu = <0x17>;
coresight-name = "coresight-etm3";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x9a>;
linux,phandle = <0x91>;
phandle = <0x91>;
};
};
};
etm@7C40000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7c40000 0x1000>;
cpu = <0x18>;
coresight-name = "coresight-etm4";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x9b>;
linux,phandle = <0x92>;
phandle = <0x92>;
};
};
};
etm@7D40000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7d40000 0x1000>;
cpu = <0x19>;
coresight-name = "coresight-etm5";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x9c>;
linux,phandle = <0x93>;
phandle = <0x93>;
};
};
};
etm@7E40000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7e40000 0x1000>;
cpu = <0x1a>;
coresight-name = "coresight-etm6";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x9d>;
linux,phandle = <0x94>;
phandle = <0x94>;
};
};
};
etm@7F40000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b95d>;
reg = <0x7f40000 0x1000>;
cpu = <0x1b>;
coresight-name = "coresight-etm7";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0x9e>;
linux,phandle = <0x95>;
phandle = <0x95>;
};
};
};
cti@6010000 {
compatible = "arm,coresight-cti";
reg = <0x6010000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti0";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6011000 {
compatible = "arm,coresight-cti";
reg = <0x6011000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti1";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6012000 {
compatible = "arm,coresight-cti";
reg = <0x6012000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti2";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6013000 {
compatible = "arm,coresight-cti";
reg = <0x6013000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti3";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6014000 {
compatible = "arm,coresight-cti";
reg = <0x6014000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti4";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6015000 {
compatible = "arm,coresight-cti";
reg = <0x6015000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti5";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6016000 {
compatible = "arm,coresight-cti";
reg = <0x6016000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti6";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6017000 {
compatible = "arm,coresight-cti";
reg = <0x6017000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti7";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6018000 {
compatible = "arm,coresight-cti";
reg = <0x6018000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti8";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@6019000 {
compatible = "arm,coresight-cti";
reg = <0x6019000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti9";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@601a000 {
compatible = "arm,coresight-cti";
reg = <0x601a000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti10";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@601b000 {
compatible = "arm,coresight-cti";
reg = <0x601b000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti11";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@601c000 {
compatible = "arm,coresight-cti";
reg = <0x601c000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti12";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@601d000 {
compatible = "arm,coresight-cti";
reg = <0x601d000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti13";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@601e000 {
compatible = "arm,coresight-cti";
reg = <0x601e000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti14";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@601f000 {
compatible = "arm,coresight-cti";
reg = <0x601f000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti15";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7820000 {
compatible = "arm,coresight-cti";
reg = <0x7820000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu0";
cpu = <0x14>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7920000 {
compatible = "arm,coresight-cti";
reg = <0x7920000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu1";
cpu = <0x15>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7a20000 {
compatible = "arm,coresight-cti";
reg = <0x7a20000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu2";
cpu = <0x16>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7b20000 {
compatible = "arm,coresight-cti";
reg = <0x7b20000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu3";
cpu = <0x17>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7c20000 {
compatible = "arm,coresight-cti";
reg = <0x7c20000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu4";
cpu = <0x18>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7d20000 {
compatible = "arm,coresight-cti";
reg = <0x7d20000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu5";
cpu = <0x19>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7e20000 {
compatible = "arm,coresight-cti";
reg = <0x7e20000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu6";
cpu = <0x1a>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
cti@7f20000 {
compatible = "arm,coresight-cti";
reg = <0x7f20000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-cpu7";
cpu = <0x1b>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
};
funnel@6005000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b908>;
reg = <0x6005000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-qatb";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0x9f>;
linux,phandle = <0x83>;
phandle = <0x83>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0xa0>;
linux,phandle = <0xa1>;
phandle = <0xa1>;
};
};
};
};
tpda@6004000 {
compatible = "qcom,coresight-tpda";
reg = <0x6004000 0x1000>;
reg-names = "tpda-base";
coresight-name = "coresight-tpda";
qcom,tpda-atid = <0x41>;
qcom,bc-elem-size = <0x7 0x20 0x9 0x20>;
qcom,tc-elem-size = <0x3 0x20 0x6 0x20 0x9 0x20>;
qcom,dsb-elem-size = <0x7 0x20 0x9 0x20>;
qcom,cmb-elem-size = <0x3 0x20 0x4 0x20 0x5 0x20 0x9 0x40>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xa1>;
linux,phandle = <0xa0>;
phandle = <0xa0>;
};
};
port@1 {
reg = <0x3>;
endpoint {
slave-mode;
remote-endpoint = <0xa2>;
linux,phandle = <0xa7>;
phandle = <0xa7>;
};
};
port@2 {
reg = <0x4>;
endpoint {
slave-mode;
remote-endpoint = <0xa3>;
linux,phandle = <0xa8>;
phandle = <0xa8>;
};
};
port@3 {
reg = <0x5>;
endpoint {
slave-mode;
remote-endpoint = <0xa4>;
linux,phandle = <0xa9>;
phandle = <0xa9>;
};
};
port@4 {
reg = <0x7>;
endpoint {
slave-mode;
remote-endpoint = <0xa5>;
linux,phandle = <0xaa>;
phandle = <0xaa>;
};
};
port@5 {
reg = <0x9>;
endpoint {
slave-mode;
remote-endpoint = <0xa6>;
linux,phandle = <0xab>;
phandle = <0xab>;
};
};
};
};
tpdm@7038000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7038000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-vsense";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xa7>;
linux,phandle = <0xa2>;
phandle = <0xa2>;
};
};
};
tpdm@7054000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7054000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-dcc";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xa8>;
linux,phandle = <0xa3>;
phandle = <0xa3>;
};
};
};
tpdm@704c000 {
compatible = "qcom,coresight-tpdm";
reg = <0x704c000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-prng";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xa9>;
linux,phandle = <0xa4>;
phandle = <0xa4>;
};
};
};
tpdm@71d0000 {
compatible = "qcom,coresight-tpdm";
reg = <0x71d0000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-qm";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xaa>;
linux,phandle = <0xa5>;
phandle = <0xa5>;
};
};
};
tpdm@7050000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7050000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-pimem";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xab>;
linux,phandle = <0xa6>;
phandle = <0xa6>;
};
};
};
tpda@7bc2000 {
compatible = "qcom,coresight-tpda";
reg = <0x7bc2000 0x1000>;
reg-names = "tpda-base";
coresight-name = "coresight-tpda-apss";
qcom,tpda-atid = <0x42>;
qcom,dsb-elem-size = <0x0 0x20>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xac>;
linux,phandle = <0x8c>;
phandle = <0x8c>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0xad>;
linux,phandle = <0xae>;
phandle = <0xae>;
};
};
};
};
tpdm@7bc0000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7bc0000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-apss";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xae>;
linux,phandle = <0xad>;
phandle = <0xad>;
};
};
};
tpda@7043000 {
compatible = "qcom,coresight-tpda";
reg = <0x7043000 0x1000>;
reg-names = "tpda-base";
coresight-name = "coresight-tpda-mss";
qcom,tpda-atid = <0x43>;
qcom,dsb-elem-size = <0x0 0x20>;
qcom,cmb-elem-size = <0x0 0x20>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xaf>;
linux,phandle = <0x87>;
phandle = <0x87>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0xb0>;
linux,phandle = <0xb1>;
phandle = <0xb1>;
};
};
};
};
tpdm@7042000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7042000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-mss";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xb1>;
linux,phandle = <0xb0>;
phandle = <0xb0>;
};
};
};
tpda@7191000 {
compatible = "qcom,coresight-tpda";
reg = <0x7191000 0x1000>;
reg-names = "tpda-base";
coresight-name = "coresight-tpda-nav";
qcom,tpda-atid = <0x44>;
qcom,cmb-elem-size = <0x0 0x20>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xb2>;
linux,phandle = <0x86>;
phandle = <0x86>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0xb3>;
linux,phandle = <0xb4>;
phandle = <0xb4>;
};
};
};
};
tpdm@7190000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7190000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-nav";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xb4>;
linux,phandle = <0xb3>;
phandle = <0xb3>;
};
};
};
tpda@7b92000 {
compatible = "qcom,coresight-tpda";
reg = <0x7b92000 0x1000>;
reg-names = "tpda-base";
coresight-name = "coresight-tpda-olc";
qcom,tpda-atid = <0x45>;
qcom,cmb-elem-size = <0x0 0x40>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xb5>;
linux,phandle = <0x8b>;
phandle = <0x8b>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0xb6>;
linux,phandle = <0xb7>;
phandle = <0xb7>;
};
};
};
};
tpdm@7b90000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7b90000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-olc";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xb7>;
linux,phandle = <0xb6>;
phandle = <0xb6>;
};
};
};
funnel@7083000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x3b908>;
reg = <0x7083000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-spss";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "apb_pclk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xb8>;
linux,phandle = <0x82>;
phandle = <0x82>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0xb9>;
linux,phandle = <0xba>;
phandle = <0xba>;
};
};
};
};
tpda@7082000 {
compatible = "qcom,coresight-tpda";
reg = <0x7082000 0x1000>;
reg-names = "tpda-base";
coresight-name = "coresight-tpda-spss";
qcom,tpda-atid = <0x46>;
qcom,dsb-elem-size = <0x0 0x20>;
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xba>;
linux,phandle = <0xb9>;
phandle = <0xb9>;
};
};
port@1 {
reg = <0x0>;
endpoint {
slave-mode;
remote-endpoint = <0xbb>;
linux,phandle = <0xbc>;
phandle = <0xbc>;
};
};
};
};
tpdm@7080000 {
compatible = "qcom,coresight-tpdm";
reg = <0x7080000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-spss";
clocks = <0x25 0x1492202a 0x25 0xdd121669>;
clock-names = "core_clk", "core_a_clk";
port {
endpoint {
remote-endpoint = <0xbc>;
linux,phandle = <0xbb>;
phandle = <0xbb>;
};
};
};
ad-hoc-bus {
compatible = "qcom,msm-bus-device";
reg = <0x1620000 0x40000 0x1000000 0x80000 0x1500000 0x10000 0x1660000 0x60000 0x1700000 0x60000 0x17900000 0x10000 0x1740000 0x10000>;
reg-names = "snoc-base", "bimc-base", "cnoc-base", "a1noc-base", "a2noc-base", "gnoc-base", "mnoc-base";
fab-a1noc {
cell-id = <0x1802>;
label = "fab-a1noc";
qcom,fab-dev;
qcom,base-name = "a1noc-base";
qcom,bypass-qos-prg;
qcom,bus-type = <0x1>;
qcom,qos-off = <0x1000>;
qcom,base-offset = <0x9000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <0x25 0x49abba8 0x25 0xc12e4220>;
linux,phandle = <0xbe>;
phandle = <0xbe>;
};
fab-a2noc {
cell-id = <0x1803>;
label = "fab-a2noc";
qcom,fab-dev;
qcom,base-name = "a2noc-base";
qcom,bypass-qos-prg;
qcom,bus-type = <0x1>;
qcom,qos-off = <0x1000>;
qcom,base-offset = <0x5000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <0x25 0xaa681404 0x25 0xcab67089>;
linux,phandle = <0xc0>;
phandle = <0xc0>;
};
fab-bimc {
cell-id = <0x0>;
label = "fab-bimc";
qcom,fab-dev;
qcom,base-name = "bimc-base";
qcom,bus-type = <0x2>;
qcom,bypass-qos-prg;
qcom,util-fact = <0x99>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <0x25 0x4b80bf00 0x25 0x4b25668a>;
linux,phandle = <0xc3>;
phandle = <0xc3>;
};
fab-cnoc {
cell-id = <0x1400>;
label = "fab-cnoc";
qcom,fab-dev;
qcom,base-name = "cnoc-base";
qcom,bypass-qos-prg;
qcom,bus-type = <0x1>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <0x25 0xd5ccb7f4 0x25 0xd8fe2ccc>;
linux,phandle = <0xeb>;
phandle = <0xeb>;
};
fab-cr_virt {
cell-id = <0x1805>;
label = "fab-cr_virt";
qcom,virt-dev;
qcom,base-name = "cr_virt-base";
qcom,bypass-qos-prg;
};
fab-gnoc {
cell-id = <0x1804>;
label = "fab-gnoc";
qcom,fab-dev;
qcom,virt-dev;
qcom,base-name = "gnoc-base";
qcom,bypass-qos-prg;
clock-names = "bus_clk", "bus_a_clk";
clocks = <0x25 0x4b80bf00 0x25 0x4b25668a>;
linux,phandle = <0xef>;
phandle = <0xef>;
};
fab-mnoc {
cell-id = <0x800>;
label = "fab-mnoc";
qcom,fab-dev;
qcom,base-name = "mnoc-base";
qcom,bypass-qos-prg;
qcom,bus-type = <0x1>;
qcom,qos-off = <0x1000>;
qcom,base-offset = <0x4000>;
qcom,util-fact = <0x99>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <0x25 0xdb4b31e6 0x25 0xd4970614>;
linux,phandle = <0xfb>;
phandle = <0xfb>;
};
fab-snoc {
cell-id = <0x400>;
label = "fab-snoc";
qcom,fab-dev;
qcom,base-name = "snoc-base";
qcom,bypass-qos-prg;
qcom,bus-type = <0x1>;
qcom,qos-off = <0x1000>;
qcom,base-offset = <0x5000>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <0x25 0x2c341aa0 0x25 0x8fcef2af>;
linux,phandle = <0x102>;
phandle = <0x102>;
};
mas-pcie-0 {
cell-id = <0x2d>;
label = "mas-pcie-0";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x1>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbd>;
qcom,prio1 = <0x1>;
qcom,prio0 = <0x1>;
qcom,bus-dev = <0xbe>;
qcom,mas-rpm-id = <0x41>;
};
mas-usb3 {
cell-id = <0x3d>;
label = "mas-usb3";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x3>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbd>;
qcom,prio1 = <0x1>;
qcom,prio0 = <0x1>;
qcom,bus-dev = <0xbe>;
qcom,mas-rpm-id = <0x20>;
};
mas-ufs {
cell-id = <0x5f>;
label = "mas-ufs";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x0>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbd>;
qcom,prio1 = <0x1>;
qcom,prio0 = <0x1>;
qcom,bus-dev = <0xbe>;
qcom,mas-rpm-id = <0x44>;
};
mas-blsp-2 {
cell-id = <0x54>;
label = "mas-blsp-2";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,qport = <0x3>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbd>;
qcom,bus-dev = <0xbe>;
qcom,mas-rpm-id = <0x27>;
};
mas-cnoc-a2noc {
cell-id = <0x0>;
label = "mas-cnoc-a2noc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xbf>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x92>;
linux,phandle = <0x10e>;
phandle = <0x10e>;
};
mas-ipa {
cell-id = <0x5a>;
label = "mas-ipa";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x1>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbf>;
qcom,prio1 = <0x1>;
qcom,prio0 = <0x1>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x3b>;
};
mas-sdcc-2 {
cell-id = <0x51>;
label = "mas-sdcc-2";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,qport = <0x6>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbf>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x23>;
};
mas-sdcc-4 {
cell-id = <0x50>;
label = "mas-sdcc-4";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,qport = <0x7>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbf>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x24>;
};
mas-tsif {
cell-id = <0x52>;
label = "mas-tsif";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xbf>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x25>;
};
mas-blsp-1 {
cell-id = <0x56>;
label = "mas-blsp-1";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,qport = <0x8>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbf>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x29>;
};
mas-cr-virt-a2noc {
cell-id = <0x75>;
label = "mas-cr-virt-a2noc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,qport = <0x9>;
qcom,qos-mode = "fixed";
qcom,connections = <0xbf>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x91>;
linux,phandle = <0x111>;
phandle = <0x111>;
};
mas-gnoc-bimc {
cell-id = <0x74>;
label = "mas-gnoc-bimc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x2>;
qcom,ap-owned;
qcom,qport = <0x0>;
qcom,qos-mode = "fixed";
qcom,connections = <0xc1 0xc2>;
qcom,prio-lvl = <0x0>;
qcom,prio-rd = <0x0>;
qcom,prio-wr = <0x0>;
qcom,bus-dev = <0xc3>;
qcom,mas-rpm-id = <0x90>;
linux,phandle = <0x112>;
phandle = <0x112>;
};
mas-oxili {
cell-id = <0x1a>;
label = "mas-oxili";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x2>;
qcom,ap-owned;
qcom,qport = <0x1>;
qcom,qos-mode = "bypass";
qcom,connections = <0xc4 0xc5 0xc1 0xc2>;
qcom,bus-dev = <0xc3>;
qcom,mas-rpm-id = <0x6>;
};
mas-mnoc-bimc {
cell-id = <0x272b>;
label = "mas-mnoc-bimc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x2>;
qcom,ap-owned;
qcom,qport = <0x2>;
qcom,qos-mode = "bypass";
qcom,connections = <0xc4 0xc5 0xc1 0xc2>;
qcom,bus-dev = <0xc3>;
qcom,mas-rpm-id = <0x2>;
linux,phandle = <0x113>;
phandle = <0x113>;
};
mas-snoc-bimc {
cell-id = <0x272f>;
label = "mas-snoc-bimc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x2>;
qcom,qport = <0x3>;
qcom,qos-mode = "bypass";
qcom,connections = <0xc5 0xc1>;
qcom,bus-dev = <0xc3>;
qcom,mas-rpm-id = <0x3>;
linux,phandle = <0x114>;
phandle = <0x114>;
};
mas-snoc-cnoc {
cell-id = <0x2733>;
label = "mas-snoc-cnoc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea>;
qcom,bus-dev = <0xeb>;
qcom,mas-rpm-id = <0x34>;
linux,phandle = <0x115>;
phandle = <0x115>;
};
mas-qdss-dap {
cell-id = <0x4c>;
label = "mas-qdss-dap";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xdf 0xe9 0xea 0xec>;
qcom,bus-dev = <0xeb>;
qcom,mas-rpm-id = <0x31>;
};
mas-crypto-c0 {
cell-id = <0x37>;
label = "mas-crypto-c0";
qcom,buswidth = <0x28a>;
qcom,agg-ports = <0x1>;
qcom,connections = <0xed>;
qcom,bus-dev = <0xc0>;
qcom,mas-rpm-id = <0x17>;
};
mas-apps-proc {
cell-id = <0x1>;
label = "mas-apps-proc";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xee>;
qcom,bus-dev = <0xef>;
qcom,mas-rpm-id = <0x0>;
};
mas-cnoc-mnoc-mmss-cfg {
cell-id = <0x66>;
label = "mas-cnoc-mnoc-mmss-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x4>;
linux,phandle = <0x110>;
phandle = <0x110>;
};
mas-cnoc-mnoc-cfg {
cell-id = <0x67>;
label = "mas-cnoc-mnoc-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xfc>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x5>;
linux,phandle = <0x10f>;
phandle = <0x10f>;
};
mas-cpp {
cell-id = <0x6a>;
label = "mas-cpp";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x5>;
qcom,qos-mode = "bypass";
qcom,connections = <0xfd>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x73>;
};
mas-jpeg {
cell-id = <0x3e>;
label = "mas-jpeg";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x7>;
qcom,qos-mode = "bypass";
qcom,connections = <0xfd>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x7>;
};
mas-mdp-p0 {
cell-id = <0x16>;
label = "mas-mdp-p0";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x1>;
qcom,qos-mode = "bypass";
qcom,connections = <0xfd>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x8>;
};
mas-mdp-p1 {
cell-id = <0x17>;
label = "mas-mdp-p1";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x2>;
qcom,qos-mode = "bypass";
qcom,connections = <0xfd>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x3d>;
};
mas-rotator {
cell-id = <0x19>;
label = "mas-rotator";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x0>;
qcom,qos-mode = "bypass";
qcom,connections = <0xfd>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x78>;
};
mas-venus {
cell-id = <0x3f>;
label = "mas-venus";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x2>;
qcom,ap-owned;
qcom,qport = <0x3 0x4>;
qcom,qos-mode = "bypass";
qcom,connections = <0xfd>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x9>;
};
mas-vfe {
cell-id = <0x1d>;
label = "mas-vfe";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x6>;
qcom,qos-mode = "bypass";
qcom,connections = <0xfd>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0xb>;
};
mas-venus-vmem {
cell-id = <0x44>;
label = "mas-venus-vmem";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0xfe>;
qcom,bus-dev = <0xfb>;
qcom,mas-rpm-id = <0x79>;
};
mas-hmss {
cell-id = <0x2b>;
label = "mas-hmss";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x3>;
qcom,qos-mode = "fixed";
qcom,connections = <0xff 0x100 0x101>;
qcom,prio1 = <0x1>;
qcom,prio0 = <0x1>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x76>;
};
mas-qdss-bam {
cell-id = <0x35>;
label = "mas-qdss-bam";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x1>;
qcom,qos-mode = "fixed";
qcom,connections = <0x100 0xff 0x103 0x101>;
qcom,prio1 = <0x1>;
qcom,prio0 = <0x1>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x13>;
};
mas-snoc-cfg {
cell-id = <0x36>;
label = "mas-snoc-cfg";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,connections = <0x104>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x14>;
};
mas-bimc-snoc-0 {
cell-id = <0x2720>;
label = "mas-bimc-snoc-0";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,connections = <0xff 0x105 0x106 0x107 0x103 0x100 0x108>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x15>;
linux,phandle = <0x10c>;
phandle = <0x10c>;
};
mas-bimc-snoc-1 {
cell-id = <0x2747>;
label = "mas-bimc-snoc-1";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,connections = <0x109>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x6d>;
linux,phandle = <0x10d>;
phandle = <0x10d>;
};
mas-a1noc-snoc {
cell-id = <0x274f>;
label = "mas-a1noc-snoc";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,connections = <0xff 0x109 0x105 0x106 0x101 0x103 0x100 0x108>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x6f>;
linux,phandle = <0x10a>;
phandle = <0x10a>;
};
mas-a2noc-snoc {
cell-id = <0x2750>;
label = "mas-a2noc-snoc";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,connections = <0xff 0x109 0x105 0x106 0x101 0x107 0x103 0x100 0x108>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x70>;
linux,phandle = <0x10b>;
phandle = <0x10b>;
};
mas-qdss-etr {
cell-id = <0x3c>;
label = "mas-qdss-etr";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,qport = <0x2>;
qcom,qos-mode = "fixed";
qcom,connections = <0x100 0xff 0x103 0x101>;
qcom,prio1 = <0x1>;
qcom,prio0 = <0x1>;
qcom,bus-dev = <0x102>;
qcom,mas-rpm-id = <0x1f>;
};
slv-a1noc-snoc {
cell-id = <0x274e>;
label = "slv-a1noc-snoc";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0xbe>;
qcom,connections = <0x10a>;
qcom,slv-rpm-id = <0x8e>;
linux,phandle = <0xbd>;
phandle = <0xbd>;
};
slv-a2noc-snoc {
cell-id = <0x2751>;
label = "slv-a2noc-snoc";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0xc0>;
qcom,connections = <0x10b>;
qcom,slv-rpm-id = <0x8f>;
linux,phandle = <0xbf>;
phandle = <0xbf>;
};
slv-ebi {
cell-id = <0x200>;
label = "slv-ebi";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x2>;
qcom,bus-dev = <0xc3>;
qcom,slv-rpm-id = <0x0>;
linux,phandle = <0xc1>;
phandle = <0xc1>;
};
slv-hmss-l3 {
cell-id = <0x2a8>;
label = "slv-hmss-l3";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0xc3>;
qcom,slv-rpm-id = <0xa0>;
linux,phandle = <0xc5>;
phandle = <0xc5>;
};
slv-bimc-snoc-0 {
cell-id = <0x2721>;
label = "slv-bimc-snoc-0";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0xc3>;
qcom,connections = <0x10c>;
qcom,slv-rpm-id = <0x2>;
linux,phandle = <0xc2>;
phandle = <0xc2>;
};
slv-bimc-snoc-1 {
cell-id = <0x2748>;
label = "slv-bimc-snoc-1";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xc3>;
qcom,connections = <0x10d>;
qcom,slv-rpm-id = <0x8a>;
linux,phandle = <0xc4>;
phandle = <0xc4>;
};
slv-cnoc-a2noc {
cell-id = <0x2732>;
label = "slv-cnoc-a2noc";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,connections = <0x10e>;
qcom,slv-rpm-id = <0xd0>;
linux,phandle = <0xec>;
phandle = <0xec>;
};
slv-ssc-cfg {
cell-id = <0x2b9>;
label = "slv-ssc-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xb1>;
linux,phandle = <0xdf>;
phandle = <0xdf>;
};
slv-mpm {
cell-id = <0x218>;
label = "slv-mpm";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x3e>;
linux,phandle = <0xcb>;
phandle = <0xcb>;
};
slv-pmic-arb {
cell-id = <0x278>;
label = "slv-pmic-arb";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x3b>;
linux,phandle = <0xd8>;
phandle = <0xd8>;
};
slv-tlmm-north {
cell-id = <0x2db>;
label = "slv-tlmm-north";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xd6>;
linux,phandle = <0xea>;
phandle = <0xea>;
};
slv-pimem-cfg {
cell-id = <0x2a9>;
label = "slv-pimem-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xa7>;
linux,phandle = <0xcf>;
phandle = <0xcf>;
};
slv-imem-cfg {
cell-id = <0x273>;
label = "slv-imem-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x36>;
linux,phandle = <0xe6>;
phandle = <0xe6>;
};
slv-message-ram {
cell-id = <0x274>;
label = "slv-message-ram";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x37>;
linux,phandle = <0xc8>;
phandle = <0xc8>;
};
slv-skl {
cell-id = <0x2dd>;
label = "slv-skl";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xc4>;
linux,phandle = <0xc6>;
phandle = <0xc6>;
};
slv-bimc-cfg {
cell-id = <0x275>;
label = "slv-bimc-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x38>;
linux,phandle = <0xcc>;
phandle = <0xcc>;
};
slv-prng {
cell-id = <0x26a>;
label = "slv-prng";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x2c>;
linux,phandle = <0xd3>;
phandle = <0xd3>;
};
slv-a2noc-cfg {
cell-id = <0x2b0>;
label = "slv-a2noc-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x96>;
linux,phandle = <0xd7>;
phandle = <0xd7>;
};
slv-ipa {
cell-id = <0x2a4>;
label = "slv-ipa";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xb7>;
linux,phandle = <0xdc>;
phandle = <0xdc>;
};
slv-tcsr {
cell-id = <0x26f>;
label = "slv-tcsr";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x32>;
linux,phandle = <0xe9>;
phandle = <0xe9>;
};
slv-snoc-cfg {
cell-id = <0x282>;
label = "slv-snoc-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x46>;
linux,phandle = <0xde>;
phandle = <0xde>;
};
slv-clk-ctl {
cell-id = <0x26c>;
label = "slv-clk-ctl";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x2f>;
linux,phandle = <0xd2>;
phandle = <0xd2>;
};
slv-glm {
cell-id = <0x2d6>;
label = "slv-glm";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xd1>;
linux,phandle = <0xdd>;
phandle = <0xdd>;
};
slv-spdm {
cell-id = <0x279>;
label = "slv-spdm";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x3c>;
linux,phandle = <0xce>;
phandle = <0xce>;
};
slv-gpuss-cfg {
cell-id = <0x256>;
label = "slv-gpuss-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xb>;
linux,phandle = <0xe8>;
phandle = <0xe8>;
};
slv-cnoc-mnoc-cfg {
cell-id = <0x280>;
label = "slv-cnoc-mnoc-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,connections = <0x10f>;
qcom,slv-rpm-id = <0x42>;
linux,phandle = <0xe4>;
phandle = <0xe4>;
};
slv-qm-cfg {
cell-id = <0x2d9>;
label = "slv-qm-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xd4>;
linux,phandle = <0xd6>;
phandle = <0xd6>;
};
slv-mss-cfg {
cell-id = <0x26d>;
label = "slv-mss-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x30>;
linux,phandle = <0xe5>;
phandle = <0xe5>;
};
slv-ufs-cfg {
cell-id = <0x28a>;
label = "slv-ufs-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x5c>;
linux,phandle = <0xd9>;
phandle = <0xd9>;
};
slv-tlmm-west {
cell-id = <0x2dc>;
label = "slv-tlmm-west";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xd7>;
linux,phandle = <0xc9>;
phandle = <0xc9>;
};
slv-a1noc-cfg {
cell-id = <0x2af>;
label = "slv-a1noc-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x93>;
linux,phandle = <0xe7>;
phandle = <0xe7>;
};
slv-ahb2phy {
cell-id = <0x2ad>;
label = "slv-ahb2phy";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xa3>;
linux,phandle = <0xdb>;
phandle = <0xdb>;
};
slv-blsp-2 {
cell-id = <0x263>;
label = "slv-blsp-2";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x25>;
linux,phandle = <0xc7>;
phandle = <0xc7>;
};
slv-pdm {
cell-id = <0x267>;
label = "slv-pdm";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x29>;
linux,phandle = <0xe2>;
phandle = <0xe2>;
};
slv-usb3-0 {
cell-id = <0x247>;
label = "slv-usb3-0";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x16>;
linux,phandle = <0xd4>;
phandle = <0xd4>;
};
slv-a1noc-smmu-cfg {
cell-id = <0x2b4>;
label = "slv-a1noc-smmu-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x95>;
linux,phandle = <0xd0>;
phandle = <0xd0>;
};
slv-blsp-1 {
cell-id = <0x265>;
label = "slv-blsp-1";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x27>;
linux,phandle = <0xd1>;
phandle = <0xd1>;
};
slv-sdcc-2 {
cell-id = <0x260>;
label = "slv-sdcc-2";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x21>;
linux,phandle = <0xe0>;
phandle = <0xe0>;
};
slv-sdcc-4 {
cell-id = <0x261>;
label = "slv-sdcc-4";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x22>;
linux,phandle = <0xe1>;
phandle = <0xe1>;
};
slv-tsif {
cell-id = <0x23f>;
label = "slv-tsif";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x23>;
linux,phandle = <0xca>;
phandle = <0xca>;
};
slv-qdss-cfg {
cell-id = <0x27b>;
label = "slv-qdss-cfg";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x3f>;
linux,phandle = <0xd5>;
phandle = <0xd5>;
};
slv-tlmm-east {
cell-id = <0x2da>;
label = "slv-tlmm-east";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0xd5>;
linux,phandle = <0xcd>;
phandle = <0xcd>;
};
slv-cnoc-mnoc-mmss-cfg {
cell-id = <0x277>;
label = "slv-cnoc-mnoc-mmss-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,connections = <0x110>;
qcom,slv-rpm-id = <0x3a>;
linux,phandle = <0xe3>;
phandle = <0xe3>;
};
slv-srvc-cnoc {
cell-id = <0x286>;
label = "slv-srvc-cnoc";
qcom,buswidth = <0x4>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xeb>;
qcom,slv-rpm-id = <0x4c>;
linux,phandle = <0xda>;
phandle = <0xda>;
};
slv-cr-virt-a2noc {
cell-id = <0x2d4>;
label = "slv-cr-virt-a2noc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xc0>;
qcom,connections = <0x111>;
qcom,slv-rpm-id = <0xcf>;
linux,phandle = <0xed>;
phandle = <0xed>;
};
slv-gnoc-bimc {
cell-id = <0x2d7>;
label = "slv-gnoc-bimc";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xef>;
qcom,connections = <0x112>;
qcom,slv-rpm-id = <0xd2>;
linux,phandle = <0xee>;
phandle = <0xee>;
};
slv-camera-cfg {
cell-id = <0x24d>;
label = "slv-camera-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0x3>;
linux,phandle = <0xf3>;
phandle = <0xf3>;
};
slv-camera-throttle-cfg {
cell-id = <0x2c5>;
label = "slv-camera-throttle-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0x9a>;
linux,phandle = <0xf0>;
phandle = <0xf0>;
};
slv-misc-cfg {
cell-id = <0x252>;
label = "slv-misc-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0x8>;
linux,phandle = <0xf2>;
phandle = <0xf2>;
};
slv-venus-throttle-cfg {
cell-id = <0x2b8>;
label = "slv-venus-throttle-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0xb2>;
linux,phandle = <0xf5>;
phandle = <0xf5>;
};
slv-venus-cfg {
cell-id = <0x254>;
label = "slv-venus-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0xa>;
linux,phandle = <0xf1>;
phandle = <0xf1>;
};
slv-vmem-cfg {
cell-id = <0x2c4>;
label = "slv-vmem-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0xb4>;
qcom,enable-only-clk;
clock-names = "node_clk";
clocks = <0x26 0xd8b7278f>;
linux,phandle = <0xf8>;
phandle = <0xf8>;
};
slv-mmss-clk-xpu-cfg {
cell-id = <0x258>;
label = "slv-mmss-clk-xpu-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0xd>;
linux,phandle = <0xf9>;
phandle = <0xf9>;
};
slv-mmss-clk-cfg {
cell-id = <0x257>;
label = "slv-mmss-clk-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0xc>;
linux,phandle = <0xf7>;
phandle = <0xf7>;
};
slv-display-cfg {
cell-id = <0x24e>;
label = "slv-display-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0x4>;
linux,phandle = <0xf6>;
phandle = <0xf6>;
};
slv-display-throttle-cfg {
cell-id = <0x2bc>;
label = "slv-display-throttle-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0x9c>;
linux,phandle = <0xf4>;
phandle = <0xf4>;
};
slv-smmu-cfg {
cell-id = <0x2d2>;
label = "slv-smmu-cfg";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0xcd>;
linux,phandle = <0xfa>;
phandle = <0xfa>;
};
slv-mnoc-bimc {
cell-id = <0x272c>;
label = "slv-mnoc-bimc";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x2>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,connections = <0x113>;
qcom,slv-rpm-id = <0x10>;
qcom,enable-only-clk;
clock-names = "node_clk";
clocks = <0x25 0xdb4b31e6>;
linux,phandle = <0xfd>;
phandle = <0xfd>;
};
slv-vmem {
cell-id = <0x2c6>;
label = "slv-vmem";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0xb3>;
clock-names = "node_clk";
clocks = <0x26 0xd8b7278f>;
linux,phandle = <0xfe>;
phandle = <0xfe>;
};
slv-srvc-mnoc {
cell-id = <0x25b>;
label = "slv-srvc-mnoc";
qcom,buswidth = <0x8>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0xfb>;
qcom,slv-rpm-id = <0x11>;
linux,phandle = <0xfc>;
phandle = <0xfc>;
};
slv-hmss {
cell-id = <0x2a1>;
label = "slv-hmss";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0x14>;
linux,phandle = <0x106>;
phandle = <0x106>;
};
slv-lpass {
cell-id = <0x20a>;
label = "slv-lpass";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0x15>;
linux,phandle = <0x105>;
phandle = <0x105>;
};
slv-wlan {
cell-id = <0x2d3>;
label = "slv-wlan";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0xce>;
linux,phandle = <0x107>;
phandle = <0x107>;
};
slv-snoc-bimc {
cell-id = <0x2730>;
label = "slv-snoc-bimc";
qcom,buswidth = <0x20>;
qcom,agg-ports = <0x2>;
qcom,bus-dev = <0x102>;
qcom,connections = <0x114>;
qcom,slv-rpm-id = <0x18>;
linux,phandle = <0x101>;
phandle = <0x101>;
};
slv-snoc-cnoc {
cell-id = <0x2734>;
label = "slv-snoc-cnoc";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0x102>;
qcom,connections = <0x115>;
qcom,slv-rpm-id = <0x19>;
linux,phandle = <0x103>;
phandle = <0x103>;
};
slv-imem {
cell-id = <0x249>;
label = "slv-imem";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0x1a>;
linux,phandle = <0x100>;
phandle = <0x100>;
};
slv-pimem {
cell-id = <0x2c8>;
label = "slv-pimem";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0xa6>;
linux,phandle = <0xff>;
phandle = <0xff>;
};
slv-qdss-stm {
cell-id = <0x24c>;
label = "slv-qdss-stm";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0x1e>;
linux,phandle = <0x108>;
phandle = <0x108>;
};
slv-pcie-0 {
cell-id = <0x299>;
label = "slv-pcie-0";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,ap-owned;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0x54>;
linux,phandle = <0x109>;
phandle = <0x109>;
};
slv-srvc-snoc {
cell-id = <0x24b>;
label = "slv-srvc-snoc";
qcom,buswidth = <0x10>;
qcom,agg-ports = <0x1>;
qcom,bus-dev = <0x102>;
qcom,slv-rpm-id = <0x1d>;
linux,phandle = <0x104>;
phandle = <0x104>;
};
};
qcom,kgsl-hyp {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xd>;
qcom,firmware-name = "a530_zap";
memory-region = <0x35>;
};
qcom,kgsl-busmon {
label = "kgsl-busmon";
compatible = "qcom,kgsl-busmon";
};
qcom,gpubw {
compatible = "qcom,devbw";
governor = "bw_vbif";
qcom,src-dst-ports = <0x1a 0x200>;
qcom,active-only;
qcom,bw-tbl = <0x0 0x2fa 0x478 0x5f5 0x8f0 0xc47 0x104d 0x144b 0x16e3 0x1e4f 0x269f 0x2e57 0x35c3>;
linux,phandle = <0x116>;
phandle = <0x116>;
};
qcom,kgsl-3d0@5000000 {
label = "kgsl-3d0";
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
status = "ok";
reg = <0x5000000 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <0x0 0x12c 0x0>;
interrupt-names = "kgsl_3d0_irq";
qcom,id = <0x0>;
qcom,chipid = <0x5040000>;
qcom,gpu-efuse-leakage = <0x70130 0x18>;
qcom,base-leakage-coefficient = <0x22>;
qcom,lm-limit = <0x1770>;
qcom,initial-pwrlevel = <0x4>;
qcom,idle-timeout = <0x50>;
qcom,deep-nap-timeout = <0x2>;
qcom,strtstp-sleepwake;
qcom,highest-bank-bit = <0xf>;
qcom,snapshot-size = <0x100000>;
clocks = <0x28 0x95f01bd5 0x25 0x72f20a57 0x28 0x58a0a7ca 0x25 0x3edd69ad 0x25 0x3909459b 0x28 0xb2678e80 0x28 0x7bd750e8>;
clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", "mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk";
qcom,gpubw-dev = <0x116>;
qcom,bus-control;
qcom,msm-bus,name = "grp3d";
qcom,msm-bus,num-cases = <0xd>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x0 0x0 0x1a 0x200 0x0 0xc3500 0x1a 0x200 0x0 0x124f80 0x1a 0x200 0x0 0x186a00 0x1a 0x200 0x0 0x249f00 0x1a 0x200 0x0 0x324b00 0x1a 0x200 0x0 0x42c5c0 0x1a 0x200 0x0 0x532140 0x1a 0x200 0x0 0x5dc000 0x1a 0x200 0x0 0x7c2540 0x1a 0x200 0x0 0x9e3400 0x1a 0x200 0x0 0xbdd1c0 0x1a 0x200 0x0 0xdc3700>;
regulator-names = "vddcx", "vdd";
vddcx-supply = <0x72>;
vdd-supply = <0x117>;
linux,phandle = <0x30>;
phandle = <0x30>;
qcom,gpu-mempools {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "qcom,gpu-mempools";
qcom,gpu-mempool@0 {
reg = <0x0>;
qcom,mempool-page-size = <0x1000>;
qcom,mempool-reserved = <0x800>;
qcom,mempool-allocate;
};
qcom,gpu-mempool@1 {
reg = <0x1>;
qcom,mempool-page-size = <0x2000>;
qcom,mempool-reserved = <0x400>;
qcom,mempool-allocate;
};
qcom,gpu-mempool@2 {
reg = <0x2>;
qcom,mempool-page-size = <0x10000>;
qcom,mempool-reserved = <0x100>;
};
qcom,gpu-mempool@3 {
reg = <0x3>;
qcom,mempool-page-size = <0x100000>;
qcom,mempool-reserved = <0x20>;
};
};
qcom,gpu-pwrlevels {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "qcom,gpu-pwrlevels";
qcom,gpu-pwrlevel@0 {
reg = <0x0>;
qcom,gpu-freq = <0x26be3680>;
qcom,bus-freq = <0xc>;
qcom,bus-min = <0xb>;
qcom,bus-max = <0xc>;
};
qcom,gpu-pwrlevel@1 {
reg = <0x1>;
qcom,gpu-freq = <0x1e0a6e00>;
qcom,bus-freq = <0xb>;
qcom,bus-min = <0xa>;
qcom,bus-max = <0xc>;
};
qcom,gpu-pwrlevel@2 {
reg = <0x2>;
qcom,gpu-freq = <0x18054ac0>;
qcom,bus-freq = <0xa>;
qcom,bus-min = <0x9>;
qcom,bus-max = <0xb>;
};
qcom,gpu-pwrlevel@3 {
reg = <0x3>;
qcom,gpu-freq = <0x13c9eb00>;
qcom,bus-freq = <0x7>;
qcom,bus-min = <0x6>;
qcom,bus-max = <0x8>;
};
qcom,gpu-pwrlevel@4 {
reg = <0x4>;
qcom,gpu-freq = <0xef5f4c0>;
qcom,bus-freq = <0x4>;
qcom,bus-min = <0x3>;
qcom,bus-max = <0x5>;
};
qcom,gpu-pwrlevel@5 {
reg = <0x5>;
qcom,gpu-freq = <0xa3140c0>;
qcom,bus-freq = <0x3>;
qcom,bus-min = <0x1>;
qcom,bus-max = <0x4>;
};
qcom,gpu-pwrlevel@6 {
reg = <0x6>;
qcom,gpu-freq = <0x19bfcc0>;
qcom,bus-freq = <0x0>;
qcom,bus-min = <0x0>;
qcom,bus-max = <0x0>;
};
};
};
qcom,kgsl-iommu {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x5040000 0x10000>;
qcom,protect = <0x40000 0x10000>;
qcom,micro-mmu-control = <0x6000>;
clocks = <0x25 0x72f20a57 0x25 0x3edd69ad 0x25 0x3909459b>;
clock-names = "iface_clk", "mem_clk", "mem_iface_clk";
qcom,secure_align_mask = <0xfff>;
qcom,retention;
qcom,hyp_secure_alloc;
gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
label = "gfx3d_user";
iommus = <0x118 0x0>;
qcom,gpu-offset = <0x48000>;
};
gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <0x118 0x2>;
};
};
qcom,mdss_mdp@c900000 {
compatible = "qcom,mdss_mdp";
reg = <0xc900000 0x90000 0xc9b0000 0x1040>;
reg-names = "mdp_phys", "vbif_phys";
interrupts = <0x0 0x53 0x0>;
interrupt-controller;
#interrupt-cells = <0x1>;
vdd-supply = <0x119>;
qcom,msm-bus,name = "mdss_mdp";
qcom,msm-bus,num-cases = <0x3>;
qcom,msm-bus,num-paths = <0x2>;
qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x17 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800>;
qcom,mdss-ab-factor = <0x1 0x1>;
qcom,mdss-ib-factor = <0x1 0x1>;
qcom,mdss-clk-factor = <0x69 0x64>;
qcom,max-mixer-width = <0xa00>;
qcom,max-pipe-width = <0xa00>;
qcom,mdss-vbif-qos-rt-setting = <0x1 0x2 0x2 0x2>;
qcom,mdss-has-panic-ctrl;
qcom,mdss-per-pipe-panic-luts = <0xf 0xffff 0xfffc 0xff00>;
qcom,mdss-mdp-reg-offset = <0x1000>;
qcom,max-bandwidth-low-kbps = <0x663be0>;
qcom,max-bandwidth-high-kbps = <0x663be0>;
qcom,max-bandwidth-per-pipe-kbps = <0x249f00>;
qcom,max-clk-rate = <0x18964020>;
qcom,mdss-default-ot-rd-limit = <0x10>;
qcom,mdss-default-ot-wr-limit = <0x10>;
qcom,mdss-dram-channels = <0x2>;
qcom,mdss-pipe-vig-off = <0x5000 0x7000 0x9000 0xb000>;
qcom,mdss-pipe-dma-off = <0x25000 0x27000 0x29000 0x2b000>;
qcom,mdss-pipe-cursor-off = <0x35000 0x37000>;
qcom,mdss-pipe-vig-xin-id = <0x0 0x4 0x8 0xc>;
qcom,mdss-pipe-dma-xin-id = <0x1 0x5 0x9 0xd>;
qcom,mdss-pipe-cursor-xin-id = <0x2 0xa>;
qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0x0 0x0 0x2b4 0x0 0x0 0x2bc 0x0 0x0 0x2c4 0x0 0x0>;
qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 0x8 0xc 0x2b4 0x8 0xc 0x2c4 0x8 0xc 0x2c4 0xc 0xe>;
qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 0x10 0xf 0x3b0 0x10 0xf>;
qcom,mdss-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800>;
qcom,mdss-mixer-intf-off = <0x45000 0x46000 0x47000 0x4a000>;
qcom,mdss-dspp-off = <0x55000 0x57000>;
qcom,mdss-wb-off = <0x66000>;
qcom,mdss-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>;
qcom,mdss-pingpong-off = <0x71000 0x71800 0x72000 0x72800>;
qcom,mdss-slave-pingpong-off = <0x73000>;
qcom,mdss-ppb-ctl-off = <0x330 0x338 0x370 0x374>;
qcom,mdss-ppb-cfg-off = <0x334 0x33c>;
qcom,mdss-has-pingpong-split;
qcom,mdss-has-separate-rotator;
qcom,mdss-ad-off = <0x79000 0x79800 0x7a000>;
qcom,mdss-cdm-off = <0x7a200>;
qcom,mdss-dsc-off = <0x81000 0x81400>;
qcom,mdss-wfd-mode = "intf";
qcom,mdss-has-source-split;
qcom,mdss-highest-bank-bit = <0x2>;
qcom,mdss-has-decimation;
qcom,mdss-idle-power-collapse-enabled;
clocks = <0x26 0x85d37ab5 0x26 0xdf04fc1d 0x26 0x6dc1f8f1 0x26 0x43539b0e 0x26 0x629b36dc>;
clock-names = "iface_clk", "bus_clk", "core_clk_src", "core_clk", "vsync_clk";
qcom,regs-dump-mdp = <0x1000 0x1454 0x2000 0x2064 0x2200 0x2264 0x2400 0x2464 0x2600 0x2664 0x2800 0x2864 0x5000 0x5150 0x5200 0x5230 0x7000 0x7150 0x7200 0x7230 0x9000 0x9150 0x9200 0x9230 0xb000 0xb150 0xb200 0xb230 0x25000 0x25184 0x27000 0x27184 0x29000 0x29184 0x2b000 0x2b184 0x35000 0x35150 0x37000 0x37150 0x45000 0x452bc 0x46000 0x462bc 0x47000 0x472bc 0x48000 0x482bc 0x49000 0x492bc 0x4a000 0x4a2bc 0x55000 0x5522c 0x57000 0x5722c 0x66000 0x662c0 0x6b000 0x6b268 0x6b800 0x6ba68 0x6c000 0x6c268 0x6c800 0x6ca68 0x71000 0x710d4 0x71800 0x718d4 0x73000 0x730d4 0x81000 0x81140 0x81400 0x81540>;
qcom,regs-dump-names-mdp = "MDP", "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4", "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1", "VIG2_SSPP", "VIG2", "VIG3_SSPP", "VIG3", "DMA0_SSPP", "DMA1_SSPP", "DMA2_SSPP", "DMA3_SSPP", "CURSOR0_SSPP", "CURSOR1_SSPP", "LAYER_0", "LAYER_1", "LAYER_2", "LAYER_3", "LAYER_4", "LAYER_5", "DSPP_0", "DSPP_1", "WB_2", "INTF_0", "INTF_1", "INTF_2", "INTF_3", "PP_0", "PP_1", "PP_4", "DSC_0", "DSC_1";
qcom,mdss-prefill-outstanding-buffer-bytes = <0x0>;
qcom,mdss-prefill-y-buffer-bytes = <0x0>;
qcom,mdss-prefill-scaler-buffer-lines-bilinear = <0x2>;
qcom,mdss-prefill-scaler-buffer-lines-caf = <0x4>;
qcom,mdss-prefill-post-scaler-buffer-pixels = <0xa00>;
qcom,mdss-prefill-pingpong-buffer-pixels = <0x1400>;
linux,phandle = <0x11b>;
phandle = <0x11b>;
qcom,mdss-pp-offsets {
qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
qcom,mdss-sspp-vig-pcc-off = <0x1780>;
qcom,mdss-sspp-rgb-pcc-off = <0x380>;
qcom,mdss-sspp-dma-pcc-off = <0x380>;
qcom,mdss-lm-pgc-off = <0x3c0>;
qcom,mdss-dspp-gamut-off = <0x1600>;
qcom,mdss-dspp-pcc-off = <0x1700>;
qcom,mdss-dspp-pgc-off = <0x17c0>;
};
qcom,mdss-scaler-offsets {
qcom,mdss-vig-scaler-off = <0xa00>;
qcom,mdss-vig-scaler-lut-off = <0xb00>;
qcom,mdss-has-dest-scaler;
qcom,mdss-dest-block-off = <0x61000>;
qcom,mdss-dest-scaler-off = <0x800 0x1000>;
qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>;
};
qcom,smmu_mdp_unsec_cb {
compatible = "qcom,smmu_mdp_unsec";
iommus = <0x71 0x0>;
gdsc-mmagic-mdss-supply = <0x70>;
clocks = <0x26 0x4825baf4 0x26 0xc365ac39>;
clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";
};
qcom,smmu_mdp_sec_cb {
compatible = "qcom,smmu_mdp_sec";
iommus = <0x71 0x1>;
gdsc-mmagic-mdss-supply = <0x70>;
clocks = <0x26 0x4825baf4 0x26 0xc365ac39>;
clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";
};
qcom,mdss_fb_primary {
cell-index = <0x0>;
compatible = "qcom,mdss-fb";
};
qcom,mdss_fb_wfd {
cell-index = <0x1>;
compatible = "qcom,mdss-fb";
linux,phandle = <0x11a>;
phandle = <0x11a>;
};
};
qcom,mdss_wb_panel {
compatible = "qcom,mdss_wb";
qcom,mdss_pan_res = <0x280 0x1e0>;
qcom,mdss_pan_bpp = <0x18>;
qcom,mdss-fb-map = <0x11a>;
};
qcom,mdss_rotator {
compatible = "qcom,sde_rotator";
reg = <0xc900000 0xab100 0xc9b8000 0x1040>;
reg-names = "mdp_phys", "rot_vbif_phys";
qcom,mdss-rot-mode = <0x1>;
qcom,mdss-highest-bank-bit = <0x2>;
qcom,msm-bus,name = "mdss_rotator";
qcom,msm-bus,num-cases = <0x3>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x19 0x200 0x0 0x0 0x19 0x200 0x0 0x61a800 0x19 0x200 0x0 0x61a800>;
rot-vdd-supply = <0x119>;
qcom,supply-names = "rot-vdd";
clocks = <0x26 0x85d37ab5 0x26 0xce49b56c 0x26 0xbb7e71c4 0x26 0xdf04fc1d>;
clock-names = "iface_clk", "rot_core_clk", "rot_clk", "axi_clk";
interrupt-parent = <0x11b>;
interrupts = <0x2 0x0>;
qcom,mdss-rot-vbif-qos-setting = <0x1 0x1 0x1 0x1>;
qcom,mdss-default-ot-rd-limit = <0x20>;
qcom,mdss-default-ot-wr-limit = <0x20>;
qcom,smmu_rot_unsec_cb {
compatible = "qcom,smmu_sde_rot_unsec";
iommus = <0x71 0xe00>;
gdsc-mdss-supply = <0x70>;
clocks = <0x26 0x4825baf4 0x26 0xc365ac39>;
clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";
};
qcom,smmu_rot_sec_cb {
compatible = "qcom,smmu_sde_rot_sec";
iommus = <0x71 0xe01>;
gdsc-mdss-supply = <0x70>;
clocks = <0x26 0x4825baf4 0x26 0xc365ac39>;
clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";
};
};
pinctrl@03400000 {
compatible = "qcom,msmcobalt-pinctrl";
reg = <0x3400000 0xc00000>;
interrupts = <0x0 0xd0 0x0>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0x14f>;
phandle = <0x14f>;
uart_console_active {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart8_a";
};
config {
pins = "gpio4", "gpio5";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_1 {
i2c_1_active {
linux,phandle = <0x11d>;
phandle = <0x11d>;
mux {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
};
config {
pins = "gpio2", "gpio3";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_1_sleep {
linux,phandle = <0x11e>;
phandle = <0x11e>;
mux {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
};
config {
pins = "gpio2", "gpio3";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_2 {
i2c_2_active {
linux,phandle = <0x11f>;
phandle = <0x11f>;
mux {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
};
config {
pins = "gpio32", "gpio33";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_2_sleep {
linux,phandle = <0x120>;
phandle = <0x120>;
mux {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
};
config {
pins = "gpio32", "gpio33";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_3 {
i2c_3_active {
linux,phandle = <0x121>;
phandle = <0x121>;
mux {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
};
config {
pins = "gpio47", "gpio48";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_3_sleep {
linux,phandle = <0x122>;
phandle = <0x122>;
mux {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
};
config {
pins = "gpio47", "gpio48";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_4 {
i2c_4_active {
linux,phandle = <0x123>;
phandle = <0x123>;
mux {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
};
config {
pins = "gpio10", "gpio11";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_4_sleep {
linux,phandle = <0x124>;
phandle = <0x124>;
mux {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
};
config {
pins = "gpio10", "gpio11";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_5 {
i2c_5_active {
linux,phandle = <0x125>;
phandle = <0x125>;
mux {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
};
config {
pins = "gpio87", "gpio88";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_5_sleep {
linux,phandle = <0x126>;
phandle = <0x126>;
mux {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
};
config {
pins = "gpio87", "gpio88";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_6 {
i2c_6_active {
linux,phandle = <0x127>;
phandle = <0x127>;
mux {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
};
config {
pins = "gpio43", "gpio44";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_6_sleep {
linux,phandle = <0x128>;
phandle = <0x128>;
mux {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
};
config {
pins = "gpio43", "gpio44";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_7 {
i2c_7_active {
linux,phandle = <0x12a>;
phandle = <0x12a>;
mux {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
};
config {
pins = "gpio55", "gpio56";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_7_sleep {
linux,phandle = <0x12b>;
phandle = <0x12b>;
mux {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
};
config {
pins = "gpio55", "gpio56";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_8 {
i2c_8_active {
linux,phandle = <0x12c>;
phandle = <0x12c>;
mux {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
};
config {
pins = "gpio6", "gpio7";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_8_sleep {
linux,phandle = <0x12d>;
phandle = <0x12d>;
mux {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
};
config {
pins = "gpio6", "gpio7";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_9 {
i2c_9_active {
linux,phandle = <0x12e>;
phandle = <0x12e>;
mux {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
};
config {
pins = "gpio51", "gpio52";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_9_sleep {
linux,phandle = <0x12f>;
phandle = <0x12f>;
mux {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
};
config {
pins = "gpio51", "gpio52";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_10 {
i2c_10_active {
linux,phandle = <0x130>;
phandle = <0x130>;
mux {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
};
config {
pins = "gpio67", "gpio68";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_10_sleep {
linux,phandle = <0x131>;
phandle = <0x131>;
mux {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
};
config {
pins = "gpio67", "gpio68";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_11 {
i2c_11_active {
linux,phandle = <0x132>;
phandle = <0x132>;
mux {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
};
config {
pins = "gpio60", "gpio61";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_11_sleep {
linux,phandle = <0x133>;
phandle = <0x133>;
mux {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
};
config {
pins = "gpio60", "gpio61";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
i2c_12 {
i2c_12_active {
linux,phandle = <0x134>;
phandle = <0x134>;
mux {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
};
config {
pins = "gpio83", "gpio84";
drive-strength = <0x2>;
bias-disable;
};
};
i2c_12_sleep {
linux,phandle = <0x135>;
phandle = <0x135>;
mux {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
};
config {
pins = "gpio83", "gpio84";
drive-strength = <0x2>;
bias-pull-up;
};
};
};
spi_1 {
spi_1_active {
linux,phandle = <0x136>;
phandle = <0x136>;
mux {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "blsp_spi1";
};
config {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <0x6>;
bias-disable;
};
};
spi_1_sleep {
linux,phandle = <0x137>;
phandle = <0x137>;
mux {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "blsp_spi1";
};
config {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_2 {
spi_2_active {
linux,phandle = <0x138>;
phandle = <0x138>;
mux {
pins = "gpio31", "gpio34", "gpio32", "gpio33";
function = "blsp_spi2";
};
config {
pins = "gpio31", "gpio34", "gpio32", "gpio33";
drive-strength = <0x6>;
bias-disable;
};
};
spi_2_sleep {
linux,phandle = <0x139>;
phandle = <0x139>;
mux {
pins = "gpio31", "gpio34", "gpio32", "gpio33";
function = "blsp_spi2";
};
config {
pins = "gpio31", "gpio34", "gpio32", "gpio33";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_3 {
spi_3_active {
linux,phandle = <0x13a>;
phandle = <0x13a>;
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_spi3";
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <0x6>;
bias-disable;
};
};
spi_3_sleep {
linux,phandle = <0x13b>;
phandle = <0x13b>;
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_spi3";
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_4 {
spi_4_active {
linux,phandle = <0x13c>;
phandle = <0x13c>;
mux {
pins = "gpio8", "gpio9", "gpio10", "gpio1";
function = "blsp_spi4";
};
config {
pins = "gpio8", "gpio9", "gpio10", "gpio1";
drive-strength = <0x6>;
bias-disable;
};
};
spi_4_sleep {
linux,phandle = <0x13d>;
phandle = <0x13d>;
mux {
pins = "gpio8", "gpio9", "gpio10", "gpio1";
function = "blsp_spi4";
};
config {
pins = "gpio8", "gpio9", "gpio10", "gpio1";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_5 {
spi_5_active {
linux,phandle = <0x13e>;
phandle = <0x13e>;
mux {
pins = "gpio0", "gpio", "gpio2", "gpio3";
function = "blsp_spi5";
};
config {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
drive-strength = <0x6>;
bias-disable;
};
};
spi_5_sleep {
linux,phandle = <0x13f>;
phandle = <0x13f>;
mux {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
function = "blsp_spi5";
};
config {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_6 {
spi_6_active {
linux,phandle = <0x140>;
phandle = <0x140>;
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_spi6";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <0x6>;
bias-disable;
};
};
spi_6_sleep {
linux,phandle = <0x141>;
phandle = <0x141>;
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_spi6";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_7 {
spi_7_active {
linux,phandle = <0x142>;
phandle = <0x142>;
mux {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
function = "blsp_spi7";
};
config {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <0x6>;
bias-disable;
};
};
spi_7_sleep {
linux,phandle = <0x143>;
phandle = <0x143>;
mux {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
function = "blsp_spi7";
};
config {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_8 {
spi_8_active {
linux,phandle = <0x144>;
phandle = <0x144>;
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "blsp_spi8";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <0x6>;
bias-disable;
};
};
spi_8_sleep {
linux,phandle = <0x145>;
phandle = <0x145>;
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "blsp_spi8";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_9 {
spi_9_active {
linux,phandle = <0x146>;
phandle = <0x146>;
mux {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_spi9";
};
config {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <0x6>;
bias-disable;
};
};
spi_9_sleep {
linux,phandle = <0x147>;
phandle = <0x147>;
mux {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_spi9";
};
config {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_10 {
spi_10_active {
linux,phandle = <0x148>;
phandle = <0x148>;
mux {
pins = "gpio65", "gpio66", "gpio67", "gpio68";
function = "blsp_spi10";
};
config {
pins = "gpio65", "gpio66", "gpio67", "gpio68";
drive-strength = <0x6>;
bias-disable;
};
};
spi_10_sleep {
linux,phandle = <0x149>;
phandle = <0x149>;
mux {
pins = "gpio65", "gpio66", "gpio67", "gpio68";
function = "blsp_spi10";
};
config {
pins = "gpio65", "gpio66", "gpio67", "gpio68";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_11 {
spi_11_active {
linux,phandle = <0x14a>;
phandle = <0x14a>;
mux {
pins = "gpio58", "gpio59", "gpio60", "gpio61";
function = "blsp_spi11";
};
config {
pins = "gpio58", "gpio59", "gpio60", "gpio61";
drive-strength = <0x6>;
bias-disable;
};
};
spi_11_sleep {
linux,phandle = <0x14b>;
phandle = <0x14b>;
mux {
pins = "gpio58", "gpio59", "gpio60", "gpio61";
function = "blsp_spi11";
};
config {
pins = "gpio58", "gpio59", "gpio60", "gpio61";
drive-strength = <0x6>;
bias-disable;
};
};
};
spi_12 {
spi_12_active {
linux,phandle = <0x14c>;
phandle = <0x14c>;
mux {
pins = "gpio81", "gpio82", "gpio83", "gpio84";
function = "blsp_spi12";
};
config {
pins = "gpio81", "gpio82", "gpio83", "gpio84";
drive-strength = <0x6>;
bias-disable;
};
};
spi_12_sleep {
linux,phandle = <0x14d>;
phandle = <0x14d>;
mux {
pins = "gpio81", "gpio82", "gpio83", "gpio84";
function = "blsp_spi12";
};
config {
pins = "gpio81", "gpio82", "gpio83", "gpio84";
drive-strength = <0x6>;
bias-disable;
};
};
};
blsp1_uart1_active {
linux,phandle = <0x151>;
phandle = <0x151>;
mux {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "blsp_uart1_a";
};
config {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <0x2>;
bias-disable;
};
};
blsp1_uart1_sleep {
linux,phandle = <0x150>;
phandle = <0x150>;
mux {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
};
config {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <0x2>;
bias-disable;
};
};
blsp1_uart2_active {
linux,phandle = <0x154>;
phandle = <0x154>;
mux {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
function = "blsp_uart2_a";
};
config {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
drive-strength = <0x2>;
bias-disable;
};
};
blsp1_uart2_sleep {
linux,phandle = <0x153>;
phandle = <0x153>;
mux {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
function = "gpio";
};
config {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
drive-strength = <0x2>;
bias-disable;
};
};
blsp1_uart3_active {
linux,phandle = <0x157>;
phandle = <0x157>;
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_uart3_a";
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <0x2>;
bias-disable;
};
};
blsp1_uart3_sleep {
linux,phandle = <0x156>;
phandle = <0x156>;
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "gpio";
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <0x2>;
bias-disable;
};
};
blsp2_uart1_active {
linux,phandle = <0x15a>;
phandle = <0x15a>;
mux {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
function = "blsp_uart7_a";
};
config {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <0x2>;
bias-disable;
};
};
blsp2_uart1_sleep {
linux,phandle = <0x159>;
phandle = <0x159>;
mux {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
function = "gpio";
};
config {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <0x2>;
bias-disable;
};
};
blsp2_uart2_active {
linux,phandle = <0x15d>;
phandle = <0x15d>;
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "blsp_uart8_a";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <0x2>;
bias-disable;
};
};
blsp2_uart2_sleep {
linux,phandle = <0x15c>;
phandle = <0x15c>;
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "gpio";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <0x2>;
bias-disable;
};
};
blsp2_uart3_active {
linux,phandle = <0x160>;
phandle = <0x160>;
mux {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9_a";
};
config {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <0x2>;
bias-disable;
};
};
blsp2_uart3_sleep {
linux,phandle = <0x15f>;
phandle = <0x15f>;
mux {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "gpio";
};
config {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <0x2>;
bias-disable;
};
};
};
qcom,sps-dma@0xc144000 {
#dma-cells = <0x4>;
compatible = "qcom,sps-dma";
reg = <0xc144000 0x25000>;
interrupts = <0x0 0xee 0x0>;
qcom,summing-threshold = <0x10>;
linux,phandle = <0x11c>;
phandle = <0x11c>;
};
qcom,sps-dma@0xc184000 {
#dma-cells = <0x4>;
compatible = "qcom,sps-dma";
reg = <0xc184000 0x25000>;
interrupts = <0x0 0xef 0x0>;
qcom,summing-threshold = <0x10>;
linux,phandle = <0x129>;
phandle = <0x129>;
};
i2c@c175000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc175000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x5f 0x0>;
dmas = <0x11c 0x6 0x40 0x20000020 0x20 0x11c 0x7 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x56>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0xc303fae9>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x11d>;
pinctrl-1 = <0x11e>;
status = "disabled";
};
i2c@c176000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc176000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x60 0x0>;
dmas = <0x11c 0x8 0x40 0x20000020 0x20 0x11c 0x9 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x56>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0x1076f220>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x11f>;
pinctrl-1 = <0x120>;
status = "disabled";
};
i2c@c177000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc177000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x61 0x0>;
dmas = <0x11c 0xa 0x40 0x20000020 0x20 0x11c 0xb 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x56>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0x9e25ac82>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x121>;
pinctrl-1 = <0x122>;
status = "disabled";
};
i2c@c178000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc178000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x62 0x0>;
dmas = <0x11c 0xc 0x40 0x20000020 0x20 0x11c 0xd 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x56>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0xd7f40f6f>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x123>;
pinctrl-1 = <0x124>;
status = "disabled";
};
i2c@c179000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc179000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x63 0x0>;
dmas = <0x11c 0xe 0x40 0x20000020 0x20 0x11c 0xf 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x56>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0xacae5604>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x125>;
pinctrl-1 = <0x126>;
status = "disabled";
};
i2c@c17a000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc17a000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x64 0x0>;
dmas = <0x11c 0x10 0x40 0x20000020 0x20 0x11c 0x11 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x56>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0x5c6ad820>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x127>;
pinctrl-1 = <0x128>;
status = "disabled";
};
i2c@c1b5000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc1b5000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x65 0x0>;
dmas = <0x129 0x6 0x40 0x20000020 0x20 0x129 0x7 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x54>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0x9ace11dd>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x12a>;
pinctrl-1 = <0x12b>;
status = "disabled";
};
i2c@c1b6000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc1b6000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x66 0x0>;
dmas = <0x129 0x8 0x40 0x20000020 0x20 0x129 0x9 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x54>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0x1bf9a57e>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x12c>;
pinctrl-1 = <0x12d>;
status = "disabled";
};
i2c@c1b7000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc1b7000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x67 0x0>;
dmas = <0x129 0xa 0x40 0x20000020 0x20 0x129 0xb 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x54>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0x336d4170>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x12e>;
pinctrl-1 = <0x12f>;
status = "disabled";
};
i2c@c1b8000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc1b8000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x68 0x0>;
dmas = <0x129 0xc 0x40 0x20000020 0x20 0x129 0xd 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x54>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0xbd22539d>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x130>;
pinctrl-1 = <0x131>;
status = "disabled";
};
i2c@c1b9000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc1b9000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x69 0x0>;
dmas = <0x129 0xe 0x40 0x20000020 0x20 0x129 0xf 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x54>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0xe2b2ce1d>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x132>;
pinctrl-1 = <0x133>;
status = "disabled";
};
i2c@c1ba000 {
compatible = "qcom,i2c-msm-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "qup_phys_addr";
reg = <0xc1ba000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0x0 0x6a 0x0>;
dmas = <0x129 0x10 0x40 0x20000020 0x20 0x129 0x11 0x20 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <0x54>;
qcom,clk-freq-out = <0x61a80>;
qcom,clk-freq-in = <0x124f800>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0x894bcea4>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <0x134>;
pinctrl-1 = <0x135>;
status = "disabled";
};
spi@c175000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc175000 0x600 0xc144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x5f 0x0 0x0 0xee 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0x6>;
qcom,bam-producer-pipe-index = <0x7>;
qcom,master-id = <0x56>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x136>;
pinctrl-1 = <0x137>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0x759a76b0>;
status = "disabled";
};
spi@c176000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc176000 0x600 0xc144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x60 0x0 0x0 0xee 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0x8>;
qcom,bam-producer-pipe-index = <0x9>;
qcom,master-id = <0x56>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x138>;
pinctrl-1 = <0x139>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0x3e77d48f>;
status = "disabled";
};
spi@c177000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc177000 0x600 0xc144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x61 0x0 0x0 0xee 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0xa>;
qcom,bam-producer-pipe-index = <0xb>;
qcom,master-id = <0x56>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x13a>;
pinctrl-1 = <0x13b>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0xfb978880>;
status = "disabled";
};
spi@c178000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc178000 0x600 0xc144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x62 0x0 0x0 0xee 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0xc>;
qcom,bam-producer-pipe-index = <0xd>;
qcom,master-id = <0x56>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x13c>;
pinctrl-1 = <0x13d>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0x80f8722f>;
status = "disabled";
};
spi@c179000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc179000 0x600 0xc144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x63 0x0 0x0 0xee 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0xe>;
qcom,bam-producer-pipe-index = <0xf>;
qcom,master-id = <0x56>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x13e>;
pinctrl-1 = <0x13f>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0xbf3e15d7>;
status = "disabled";
};
spi@c17a000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc17a000 0x600 0xc144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x64 0x0 0x0 0xee 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0x10>;
qcom,bam-producer-pipe-index = <0x11>;
qcom,master-id = <0x56>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x140>;
pinctrl-1 = <0x141>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8caa5b4f 0x25 0x780d9f85>;
status = "disabled";
};
spi@c1b5000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc1b5000 0x600 0xc184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x65 0x0 0x0 0xef 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0x6>;
qcom,bam-producer-pipe-index = <0x7>;
qcom,master-id = <0x54>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x142>;
pinctrl-1 = <0x143>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0xa32604cc>;
status = "disabled";
};
spi@c1b6000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc1b6000 0x600 0xc184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x66 0x0 0x0 0xef 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0x8>;
qcom,bam-producer-pipe-index = <0x9>;
qcom,master-id = <0x54>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x144>;
pinctrl-1 = <0x145>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0xbf54ca6d>;
status = "disabled";
};
spi@c1b7000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc1b7000 0x600 0xc184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x67 0x0 0x0 0xef 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0xa>;
qcom,bam-producer-pipe-index = <0xb>;
qcom,master-id = <0x54>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x146>;
pinctrl-1 = <0x147>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0xc68509d6>;
status = "disabled";
};
spi@c1b8000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc1b8000 0x600 0xc184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x68 0x0 0x0 0xef 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0xc>;
qcom,bam-producer-pipe-index = <0xd>;
qcom,master-id = <0x54>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x148>;
pinctrl-1 = <0x149>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0x1a72b93>;
status = "disabled";
};
spi@c1b9000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc1b9000 0x600 0xc184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x69 0x0 0x0 0xef 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0xe>;
qcom,bam-producer-pipe-index = <0xf>;
qcom,master-id = <0x54>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x14a>;
pinctrl-1 = <0x14b>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0xf40999cd>;
status = "disabled";
};
spi@c1ba000 {
compatible = "qcom,spi-qup-v2";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xc1ba000 0x600 0xc184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0x0 0x6a 0x0 0x0 0xef 0x0>;
spi-max-frequency = <0x2faf080>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <0x10>;
qcom,bam-producer-pipe-index = <0x11>;
qcom,master-id = <0x54>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <0x14c>;
pinctrl-1 = <0x14d>;
clock-names = "iface_clk", "core_clk";
clocks = <0x25 0x8f283c1d 0x25 0xfe1bd34a>;
status = "disabled";
};
uart@c16f000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0xc16f000 0x200 0xc144000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0x0>;
interrupt-parent = <0x14e>;
interrupts = <0x0 0x1 0x2>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0x0 0x1 0x0 0x6b 0x0 0x1 0x1 0x0 0xee 0x0 0x2 0x14f 0x1 0x0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0x0>;
qcom,bam-rx-ep-pipe-index = <0x1>;
qcom,master-id = <0x56>;
clock-names = "core_clk", "iface_clk";
clocks = <0x25 0xc7c62f90 0x25 0x8caa5b4f>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <0x150>;
pinctrl-1 = <0x151>;
qcom,msm-bus,name = "buart1";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
status = "disabled";
linux,phandle = <0x14e>;
phandle = <0x14e>;
};
uart@c170000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0xc170000 0x200 0xc144000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0x0>;
interrupt-parent = <0x152>;
interrupts = <0x0 0x1 0x2>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0x0 0x1 0x0 0x6c 0x0 0x1 0x1 0x0 0xee 0x0 0x2 0x14f 0x5 0x0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0x2>;
qcom,bam-rx-ep-pipe-index = <0x3>;
qcom,master-id = <0x56>;
clock-names = "core_clk", "iface_clk";
clocks = <0x25 0xf8a61c96 0x25 0x8caa5b4f>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <0x153>;
pinctrl-1 = <0x154>;
qcom,msm-bus,name = "buart2";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
status = "disabled";
linux,phandle = <0x152>;
phandle = <0x152>;
};
uart@c171000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0xc171000 0x200 0xc144000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0x0>;
interrupt-parent = <0x155>;
interrupts = <0x0 0x1 0x2>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0x0 0x1 0x0 0x6d 0x0 0x1 0x1 0x0 0xee 0x0 0x2 0x14f 0x9 0x0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0x4>;
qcom,bam-rx-ep-pipe-index = <0x5>;
qcom,master-id = <0x56>;
clock-names = "core_clk", "iface_clk";
clocks = <0x25 0xc3298bd7 0x25 0x8caa5b4f>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <0x156>;
pinctrl-1 = <0x157>;
qcom,msm-bus,name = "buart3";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
status = "disabled";
linux,phandle = <0x155>;
phandle = <0x155>;
};
uart@c1af000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0xc1af000 0x200 0xc184000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0x0>;
interrupt-parent = <0x158>;
interrupts = <0x0 0x1 0x2>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0x0 0x1 0x0 0x71 0x0 0x1 0x1 0x0 0xef 0x0 0x2 0x14f 0x1 0x0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0x0>;
qcom,bam-rx-ep-pipe-index = <0x1>;
qcom,master-id = <0x54>;
clock-names = "core_clk", "iface_clk";
clocks = <0x25 0x8c3512ff 0x25 0x8f283c1d>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <0x159>;
pinctrl-1 = <0x15a>;
qcom,msm-bus,name = "buart1";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
status = "disabled";
linux,phandle = <0x158>;
phandle = <0x158>;
};
uart@c1b0000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0xc1b0000 0x200 0xc184000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0x0>;
interrupt-parent = <0x15b>;
interrupts = <0x0 0x1 0x2>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0x0 0x1 0x0 0x72 0x0 0x1 0x1 0x0 0xef 0x0 0x2 0x14f 0x5 0x0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0x2>;
qcom,bam-rx-ep-pipe-index = <0x3>;
qcom,master-id = <0x54>;
clock-names = "core_clk", "iface_clk";
clocks = <0x25 0x1e1965a3 0x25 0x8f283c1d>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <0x15c>;
pinctrl-1 = <0x15d>;
qcom,msm-bus,name = "buart2";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
status = "disabled";
linux,phandle = <0x15b>;
phandle = <0x15b>;
};
uart@c1b1000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0xc1b1000 0x200 0xc184000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0x0>;
interrupt-parent = <0x15e>;
interrupts = <0x0 0x1 0x2>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0x0 0x1 0x0 0x73 0x0 0x1 0x1 0x0 0xef 0x0 0x2 0x14f 0x9 0x0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0x4>;
qcom,bam-rx-ep-pipe-index = <0x5>;
qcom,master-id = <0x54>;
clock-names = "core_clk", "iface_clk";
clocks = <0x25 0x382415ab 0x25 0x8f283c1d>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <0x15f>;
pinctrl-1 = <0x160>;
qcom,msm-bus,name = "buart3";
qcom,msm-bus,num-cases = <0x2>;
qcom,msm-bus,num-paths = <0x1>;
qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
status = "disabled";
linux,phandle = <0x15e>;
phandle = <0x15e>;
};
};
chosen {
};
aliases {
serial0 = "/soc/serial@0c1b0000";
sdhc2 = "/soc/sdhci@c0a4900";
i2c1 = "/soc/i2c@c175000";
i2c2 = "/soc/i2c@c176000";
i2c3 = "/soc/i2c@c177000";
i2c4 = "/soc/i2c@c178000";
i2c5 = "/soc/i2c@c179000";
i2c6 = "/soc/i2c@c17a000";
i2c7 = "/soc/i2c@c1b5000";
i2c8 = "/soc/i2c@c1b6000";
i2c9 = "/soc/i2c@c1b7000";
i2c10 = "/soc/i2c@c1b8000";
i2c11 = "/soc/i2c@c1b9000";
i2c12 = "/soc/i2c@c1ba000";
spi1 = "/soc/spi@c175000";
spi2 = "/soc/spi@c176000";
spi3 = "/soc/spi@c177000";
spi4 = "/soc/spi@c178000";
spi5 = "/soc/spi@c179000";
spi6 = "/soc/spi@c17a000";
spi7 = "/soc/spi@c1b5000";
spi8 = "/soc/spi@c1b6000";
spi9 = "/soc/spi@c1b7000";
spi10 = "/soc/spi@c1b8000";
spi11 = "/soc/spi@c1b9000";
spi12 = "/soc/spi@c1ba000";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
removed_regions@85800000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x85800000 0x0 0x5300000>;
};
peripheral_region@91900000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x91900000 0x0 0x2b00000>;
linux,phandle = <0x35>;
phandle = <0x35>;
};
modem_region@8ac00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x8ac00000 0x0 0x6d00000>;
linux,phandle = <0x4e>;
phandle = <0x4e>;
};
spss_region@8ab00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x8ab00000 0x0 0x100000>;
linux,phandle = <0x5e>;
phandle = <0x5e>;
};
adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x100000>;
size = <0x0 0x400000>;
linux,phandle = <0x73>;
phandle = <0x73>;
};
qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
linux,phandle = <0x74>;
phandle = <0x74>;
};
secure_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x200000>;
size = <0x0 0x5c00000>;
linux,phandle = <0x75>;
phandle = <0x75>;
};
};
regulator-pmcobalt-s10 {
compatible = "qcom,stub-regulator";
regulator-name = "pmcobalt_s10";
qcom,hpm-min-load = <0x186a0>;
regulator-min-microvolt = <0x55f00>;
regulator-max-microvolt = <0xe86c0>;
};
regulator-pmcobalt-s13 {
compatible = "qcom,stub-regulator";
regulator-name = "pmcobalt_s13";
qcom,hpm-min-load = <0x186a0>;
regulator-min-microvolt = <0x55f00>;
regulator-max-microvolt = <0xe86c0>;
};
regulator-pm8005-s1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8005_s1";
qcom,hpm-min-load = <0x186a0>;
regulator-min-microvolt = <0x55f00>;
regulator-max-microvolt = <0xe86c0>;
linux,phandle = <0x29>;
phandle = <0x29>;
};
regulator-pm8005-s2 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8005_s2";
qcom,hpm-min-load = <0x186a0>;
regulator-min-microvolt = <0x55f00>;
regulator-max-microvolt = <0xe86c0>;
};
regulator-pm8005-s3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8005_s3";
qcom,hpm-min-load = <0x186a0>;
regulator-min-microvolt = <0x927c0>;
regulator-max-microvolt = <0x927c0>;
linux,phandle = <0x4d>;
phandle = <0x4d>;
};
bt_wcn3990 {
compatible = "qca,wcn3990";
qca,bt-vdd-io-supply = <0x161>;
qca,bt-vdd-xtal-supply = <0x162>;
qca,bt-vdd-core-supply = <0x163>;
qca,bt-vdd-ldo-supply = <0x164>;
qca,bt-vdd-pa-supply = <0x165>;
qca,bt-chip-pwd-supply = <0x166>;
qca,bt-vdd-io-voltage-level = <0x149970 0x149970>;
qca,bt-vdd-xtal-voltage-level = <0x1f47d0 0x1f47d0>;
qca,bt-vdd-core-voltage-level = <0x1b7740 0x1b7740>;
qca,bt-vdd-ldo-voltage-level = <0x13d620 0x13d620>;
qca,bt-vdd-pa-voltage-level = <0x325aa0 0x325aa0>;
qca,bt-chip-pwd-voltage-level = <0x36ee80 0x36ee80>;
qca,bt-vdd-io-current-level = <0x1>;
qca,bt-vdd-xtal-current-level = <0x1>;
qca,bt-vdd-core-current-level = <0x1>;
qca,bt-vdd-ldo-current-level = <0x0>;
qca,bt-vdd-pa-current-level = <0x0>;
};
};